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| author | Silviu Baranga <silviu.baranga@arm.com> | 2015-09-01 11:19:15 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2015-09-01 11:19:15 +0000 |
| commit | e748c9ef5504af5e877ad170ea3ad263eb7474df (patch) | |
| tree | ea12734f8d5e6f1b2df4e992170d3eaabc42dd2e | |
| parent | 6d3f05c04bf894cb0e230dab80148a80025abb11 (diff) | |
| download | bcm5719-llvm-e748c9ef5504af5e877ad170ea3ad263eb7474df.tar.gz bcm5719-llvm-e748c9ef5504af5e877ad170ea3ad263eb7474df.zip | |
[ARM] Turn on by default interleaved access vectorization
Summary:
This change turns on by default interleaved access vectorization on ARM,
as it has shown to be beneficial on ARM.
Reviewers: rengolin
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D12146
llvm-svn: 246541
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index b5398ea947f..10d4c408966 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -52,6 +52,8 @@ public: : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), TLI(std::move(Arg.TLI)) {} + bool enableInterleavedAccessVectorization() { return true; } + /// \name Scalar TTI Implementations /// @{ diff --git a/llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll b/llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll index 0dcd8e24500..de3626b57d8 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -debug-only=loop-vectorize -loop-vectorize -instcombine -enable-interleaved-mem-accesses=true < %s 2>&1 | FileCheck %s +; RUN: opt -S -debug-only=loop-vectorize -loop-vectorize -instcombine < %s 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" |
