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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-09 13:52:33 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-09 13:52:33 +0000 |
| commit | e5ed5e2cba20d395c9028a562a4f5a4dfc019c42 (patch) | |
| tree | 3dfecbd76e678610796601bb94df80b87cda732e | |
| parent | 140fee078f6fc9706687ea55cd51e189c24903c3 (diff) | |
| download | bcm5719-llvm-e5ed5e2cba20d395c9028a562a4f5a4dfc019c42.tar.gz bcm5719-llvm-e5ed5e2cba20d395c9028a562a4f5a4dfc019c42.zip | |
[X86][MMX] Fix missing itinerary for PALIGNR
llvm-svn: 329568
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/mmx-schedule.ll | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 29814757e6c..06d30b3e62a 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -183,14 +183,14 @@ multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, u8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>, - Sched<[WriteShuffle]>; + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))], + IIC_MMX_PSHUF>, Sched<[WriteShuffle]>; def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2, u8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR64:$dst, (IntId VR64:$src1, - (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>, - Sched<[WriteShuffleLd, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))], + IIC_MMX_PSHUF>, Sched<[WriteShuffleLd, ReadAfterLd]>; } multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, diff --git a/llvm/test/CodeGen/X86/mmx-schedule.ll b/llvm/test/CodeGen/X86/mmx-schedule.ll index db17b4fa235..65271fda8df 100644 --- a/llvm/test/CodeGen/X86/mmx-schedule.ll +++ b/llvm/test/CodeGen/X86/mmx-schedule.ll @@ -2127,8 +2127,8 @@ define i64 @test_palignr(x86_mmx %a0, x86_mmx %a1, x86_mmx* %a2) optsize { ; ; ATOM-LABEL: test_palignr: ; ATOM: # %bb.0: -; ATOM-NEXT: palignr $1, %mm1, %mm0 # sched: [0:?] -; ATOM-NEXT: palignr $1, (%rdi), %mm0 # sched: [0:?] +; ATOM-NEXT: palignr $1, %mm1, %mm0 # sched: [1:1.00] +; ATOM-NEXT: palignr $1, (%rdi), %mm0 # sched: [1:1.00] ; ATOM-NEXT: movq %mm0, %rax # sched: [3:3.00] ; ATOM-NEXT: retq # sched: [79:39.50] ; |
