[llvm-mca] Remove method Instruction::isZeroLatency(). NFCI

llvm-svn: 330807

5 files changed, 11 insertions, 13 deletions

diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp
index d3efe69b89b..7a4a9d443e5 100644
--- a/llvm/tools/llvm-mca/Dispatch.cpp
+++ b/llvm/tools/llvm-mca/Dispatch.cpp
@@ -406,9 +406,13 @@ void DispatchUnit::dispatch(unsigned IID, Instruction *NewInst,
     AvailableEntries -= NumMicroOps;
   }
 
-  // Update RAW dependencies.
-  for (std::unique_ptr<ReadState> &RS : NewInst->getUses())
-    updateRAWDependencies(*RS, STI);
+  // Update RAW dependencies if this instruction is not a zero-latency
+  // instruction. The assumption is that a zero-latency instruction doesn't
+  // require to be issued to the scheduler for execution. More importantly, it
+  // doesn't have to wait on the register input operands.
+  if (NewInst->getDesc().MaxLatency)
+    for (std::unique_ptr<ReadState> &RS : NewInst->getUses())
+      updateRAWDependencies(*RS, STI);
 
   // Allocate new mappings.
   SmallVector<unsigned, 4> RegisterFiles(RAT->getNumRegisterFiles());
diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index c56a2792cd3..c45ec7d2866 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -139,8 +139,6 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
                            const MCInstrDesc &MCDesc,
                            const MCSchedClassDesc &SCDesc,
                            const MCSubtargetInfo &STI) {
-  computeMaxLatency(ID, MCDesc, SCDesc, STI);
-
   // Set if writes through this opcode may update super registers.
   // TODO: on x86-64, a 4 byte write of a general purpose register always
   // fully updates the super-register.
@@ -410,6 +408,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
 
   initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
+  computeMaxLatency(*ID, MCDesc, SCDesc, STI);
   populateWrites(*ID, MCI, MCDesc, SCDesc, STI);
   populateReads(*ID, MCI, MCDesc, SCDesc, STI);
 
@@ -431,7 +430,7 @@ InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
   const InstrDesc &D = getOrCreateInstrDesc(MCI);
   std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
 
-  // Populate Reads first.
+  // Initialize Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
     int RegID = -1;
     if (RD.OpIndex != -1) {
@@ -455,7 +454,7 @@ InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
     NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID));
   }
 
-  // Now populate writes.
+  // Initialize writes.
   for (const WriteDescriptor &WD : D.Writes) {
     unsigned RegID =
         WD.OpIndex == -1 ? WD.RegisterID : MCI.getOperand(WD.OpIndex).getReg();
diff --git a/llvm/tools/llvm-mca/Instruction.cpp b/llvm/tools/llvm-mca/Instruction.cpp
index 77b9967d940..d7ead0680ff 100644
--- a/llvm/tools/llvm-mca/Instruction.cpp
+++ b/llvm/tools/llvm-mca/Instruction.cpp
@@ -116,10 +116,6 @@ void Instruction::execute() {
     Stage = IS_EXECUTED;
 }
 
-bool Instruction::isZeroLatency() const {
-  return Desc.MaxLatency == 0 && Defs.size() == 0 && Uses.size() == 0;
-}
-
 void Instruction::update() {
   if (!isDispatched())
     return;
diff --git a/llvm/tools/llvm-mca/Instruction.h b/llvm/tools/llvm-mca/Instruction.h
index d7d26859d17..59134bc33de 100644
--- a/llvm/tools/llvm-mca/Instruction.h
+++ b/llvm/tools/llvm-mca/Instruction.h
@@ -313,7 +313,6 @@ public:
   bool isReady() const { return Stage == IS_READY; }
   bool isExecuting() const { return Stage == IS_EXECUTING; }
   bool isExecuted() const { return Stage == IS_EXECUTED; }
-  bool isZeroLatency() const;
 
   void retire() {
     assert(isExecuted() && "Instruction is in an invalid state!");
diff --git a/llvm/tools/llvm-mca/Scheduler.cpp b/llvm/tools/llvm-mca/Scheduler.cpp
index d27c22540fb..77c6745684a 100644
--- a/llvm/tools/llvm-mca/Scheduler.cpp
+++ b/llvm/tools/llvm-mca/Scheduler.cpp
@@ -263,7 +263,7 @@ void Scheduler::scheduleInstruction(unsigned Idx, Instruction &MCIS) {
   // issued immediately to the pipeline(s). Any other in-order buffered
   // resources (i.e. BufferSize=1) is consumed.
 
-  if (!MCIS.isZeroLatency() && !Resources->mustIssueImmediately(Desc)) {
+  if (Desc.MaxLatency && !Resources->mustIssueImmediately(Desc)) {
     DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Ready Queue\n");
     ReadyQueue[Idx] = &MCIS;
     return;