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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2015-02-10 23:30:14 +0000 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2015-02-10 23:30:14 +0000 |
| commit | d9f52043b141dc661b6cd3c83b60b0726b204e20 (patch) | |
| tree | 90ad1a81aed85cb524358e70a831dc517ca15fb7 | |
| parent | ca7e4702211a8cd6c65785089f6f782901323a0b (diff) | |
| download | bcm5719-llvm-d9f52043b141dc661b6cd3c83b60b0726b204e20.tar.gz bcm5719-llvm-d9f52043b141dc661b6cd3c83b60b0726b204e20.zip | |
Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function
The isSigned argument of makeLibCall function was hard-coded to false
(unsigned). This caused zero extension on MIPS64 soft float.
As the result SingleSource/Benchmarks/Stanford/FloatMM test and
SingleSource/UnitTests/2005-07-17-INT-To-FP test failed.
The solution was to use the proper argument.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7292
llvm-svn: 228765
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/mips64sinttofpsf.ll | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 4591e79316d..b5967155434 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -658,7 +658,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) { NVT, N->getOperand(0)); return TLI.makeLibCall(DAG, LC, TLI.getTypeToTransformTo(*DAG.getContext(), RVT), - &Op, 1, false, dl).first; + &Op, 1, Signed, dl).first; } diff --git a/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll new file mode 100644 index 00000000000..d3d46036f7d --- /dev/null +++ b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O0 < %s | FileCheck %s + + +define double @foo() #0 { +entry: + %x = alloca i32, align 4 + store volatile i32 -32, i32* %x, align 4 + %0 = load volatile i32* %x, align 4 + %conv = sitofp i32 %0 to double + ret double %conv + +; CHECK-NOT: dsll +; CHECK-NOT: dsrl + +} |

