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authorJim Grosbach <grosbach@apple.com>2011-09-15 16:16:50 +0000
committerJim Grosbach <grosbach@apple.com>2011-09-15 16:16:50 +0000
commitd93c4ece15e97d46446d589c3d3d267e4148fedf (patch)
tree4bd42c406df5a52f5dce4bbde6234366c70ac362
parent36618592144073ffb5748c033da85898c5cc321d (diff)
downloadbcm5719-llvm-d93c4ece15e97d46446d589c3d3d267e4148fedf.tar.gz
bcm5719-llvm-d93c4ece15e97d46446d589c3d3d267e4148fedf.zip
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
llvm-svn: 139796
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 6d565434470..245536f9450 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4942,6 +4942,9 @@ def : MnemonicAlias<"srsfd", "srsia">;
def : MnemonicAlias<"srsed", "srsib">;
def : MnemonicAlias<"srs", "srsia">;
+// QSAX == QSUBADDX
+def : MnemonicAlias<"qsubaddx", "qsax">;
+
// LDRSBT/LDRHT/LDRSHT post-index offset if optional.
// Note that the write-back output register is a dummy operand for MC (it's
// only meaningful for codegen), so we just pass zero here.
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