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author | Tim Northover <tnorthover@apple.com> | 2016-12-06 18:38:38 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2016-12-06 18:38:38 +0000 |
commit | c1a23854f31693b7dde4cb12b53df0b5cde48a1d (patch) | |
tree | 8cc0bd639f80d75dcd0ac3abda37454e262ed444 | |
parent | f50f2f3d3268b016c9940adabcadc1e8378303b5 (diff) | |
download | bcm5719-llvm-c1a23854f31693b7dde4cb12b53df0b5cde48a1d.tar.gz bcm5719-llvm-c1a23854f31693b7dde4cb12b53df0b5cde48a1d.zip |
GlobalISel: handle G_SEQUENCE fallbacks gracefully.
There were two problems:
+ AArch64 was reusing random data from its binary op tables, which is
complete nonsense for G_SEQUENCE.
+ Even when AArch64 gave up and said it couldn't handle G_SEQUENCE,
the generic code asserted.
llvm-svn: 288836
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 3 | ||||
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 4 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 9 |
3 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index 2a20e43fd4a..04bb7ca5ba9 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -367,6 +367,9 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( const RegBankSelect::MappingCost *BestCost) { assert((MBFI || !BestCost) && "Costs comparison require MBFI"); + if (!InstrMapping.isValid()) + return MappingCost::ImpossibleCost(); + // If mapped with InstrMapping, MI will have the recorded cost. MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1); bool Saturated = Cost.addLocalCost(InstrMapping.getCost()); diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index ef6c869e3ff..a5fd2fbdde1 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -494,6 +494,10 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size), /*NumOperands*/ 2}; } + case TargetOpcode::G_SEQUENCE: + // FIXME: support this, but the generic code is really not going to do + // anything sane. + return InstructionMapping(); default: break; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 304cd5eccc2..d164e2ea2f3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -59,9 +59,18 @@ false: } + ; General legalizer inability to handle types whose size wasn't a power of 2. ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type: define void @odd_type(i42* %addr) { %val42 = load i42, i42* %addr ret void } + + ; RegBankSelect crashed when given invalid mappings, and AArch64's + ; implementation produce valid-but-nonsense mappings for G_SEQUENCE. +; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping +; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping: +define void @sequence_mapping([2 x i64] %in) { + ret void +} |