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| author | Tim Northover <tnorthover@apple.com> | 2016-12-06 18:38:34 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-12-06 18:38:34 +0000 |
| commit | f50f2f3d3268b016c9940adabcadc1e8378303b5 (patch) | |
| tree | 9c3b23ade4142aedc5ce2858ebafb8ee78574062 | |
| parent | 405e25cd6a109551ce483272e16e2095bdb355f6 (diff) | |
| download | bcm5719-llvm-f50f2f3d3268b016c9940adabcadc1e8378303b5.tar.gz bcm5719-llvm-f50f2f3d3268b016c9940adabcadc1e8378303b5.zip | |
GlobalISel: allow G_SELECT instructions for pointers.
llvm-svn: 288835
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 11 |
3 files changed, 17 insertions, 5 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index c98aa68e479..97839d47271 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -488,7 +488,7 @@ public: /// \pre setBasicBlock or setMI must have been called. /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers /// with the same type. - /// \pre \p Tst must be a generic virtual register with scalar or + /// \pre \p Tst must be a generic virtual register with scalar, pointer or /// vector type. If vector then it must have the same number of /// elements as the other parameters. /// diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 69ce5033982..d46dd9f6b8f 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -392,11 +392,12 @@ MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst, unsigned Op0, unsigned Op1) { #ifndef NDEBUG - assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && + LLT ResTy = MRI->getType(Res); + assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && "invalid operand type"); - assert(MRI->getType(Res) == MRI->getType(Op0) && - MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); - if (MRI->getType(Res).isScalar()) + assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) && + "type mismatch"); + if (ResTy.isScalar() || ResTy.isPointer()) assert(MRI->getType(Tst).isScalar() && "type mismatch"); else assert(MRI->getType(Tst).isVector() && diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index f9ef78470eb..ad353bfa9ab 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -761,6 +761,17 @@ define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) { ret i32 %res } +; CHECK-LABEL: name: test_select_ptr +; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0 +; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x1 +; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x2 +; CHECK: [[RES:%[0-9]+]](p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]] +; CHECK: %x0 = COPY [[RES]] +define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) { + %res = select i1 %tst, i8* %lhs, i8* %rhs + ret i8* %res +} + ; CHECK-LABEL: name: test_fptosi ; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0 ; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0) |
