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| author | Silviu Baranga <silviu.baranga@arm.com> | 2015-09-01 11:26:46 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2015-09-01 11:26:46 +0000 |
| commit | 755ec0e027f31f0959d1eaf4b73a5e2fe92160c5 (patch) | |
| tree | 07cd13bdf517fd5bc0651efc8f27454008955661 | |
| parent | e748c9ef5504af5e877ad170ea3ad263eb7474df (diff) | |
| download | bcm5719-llvm-755ec0e027f31f0959d1eaf4b73a5e2fe92160c5.tar.gz bcm5719-llvm-755ec0e027f31f0959d1eaf4b73a5e2fe92160c5.zip | |
[AArch64] Turn on by default interleaved access vectorization
Summary:
This change turns on by default interleaved access vectorization
for AArch64.
We also clean up some tests which were spedifically enabling this
behaviour.
Reviewers: rengolin
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D12149
llvm-svn: 246542
3 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index e335c1b1c70..ed67ff897e7 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -75,6 +75,8 @@ public: /// \name Vector TTI Implementations /// @{ + bool enableInterleavedAccessVectorization() { return true; } + unsigned getNumberOfRegisters(bool Vector) { if (Vector) { if (ST->hasNEON()) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll index f16ee4171da..58315a73ec1 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll @@ -1,5 +1,5 @@ -; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=2 -force-vector-width=4 -enable-interleaved-mem-accesses=true | FileCheck %s -; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=2 -enable-interleaved-mem-accesses=true | FileCheck %s --check-prefix=FORCE-VEC +; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=2 -force-vector-width=4 | FileCheck %s +; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-gnueabi" diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll index fe61ef794a4..a0e741a3cdb 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -debug-only=loop-vectorize -loop-vectorize -instcombine -enable-interleaved-mem-accesses=true < %s 2>&1 | FileCheck %s +; RUN: opt -S -debug-only=loop-vectorize -loop-vectorize -instcombine < %s 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" |
