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| author | Robert Lougher <rob.lougher@gmail.com> | 2016-01-12 11:48:25 +0000 |
|---|---|---|
| committer | Robert Lougher <rob.lougher@gmail.com> | 2016-01-12 11:48:25 +0000 |
| commit | 6abd69a60b74584e86102d400880d2ae00932f84 (patch) | |
| tree | 36936a765869d4ba9c9523a593be52a090d48cc6 | |
| parent | 239132f452ee096d2701d7039fd148600aa37478 (diff) | |
| download | bcm5719-llvm-6abd69a60b74584e86102d400880d2ae00932f84.tar.gz bcm5719-llvm-6abd69a60b74584e86102d400880d2ae00932f84.zip | |
The isel pattern that selects the memory-register form of VCVTPH2PS
(64 to 128-bit) matches against the pattern fragment 'vzmovl_v2i64'
(a zero-extended 64-bit load).
However, a change in r248784 teaches the instruction combiner that only
the lower 64 bits of the input to a 128-bit vcvtph2ps are used. This means
the instruction combiner will ordinarily optimize away the upper 64-bit
insertelement instruction in the zero-extension and so we no longer select
the memory-register form. To fix this a new pattern has been added.
Differential Revision: http://reviews.llvm.org/D16067
llvm-svn: 257470
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/f16c-intrinsics.ll | 12 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 859ff378182..6a7c45665e9 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -8257,6 +8257,9 @@ let Predicates = [HasF16C] in { (VCVTPH2PSrm addr:$src)>; def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)), (VCVTPH2PSrm addr:$src)>; + def : Pat<(int_x86_vcvtph2ps_128 (bitconvert + (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VCVTPH2PSrm addr:$src)>; def : Pat<(store (f64 (extractelt (bc_v2f64 (v8i16 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))), diff --git a/llvm/test/CodeGen/X86/f16c-intrinsics.ll b/llvm/test/CodeGen/X86/f16c-intrinsics.ll index 485592aeac3..a78022ac550 100644 --- a/llvm/test/CodeGen/X86/f16c-intrinsics.ll +++ b/llvm/test/CodeGen/X86/f16c-intrinsics.ll @@ -61,6 +61,18 @@ define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) { ret <4 x float> %res } +define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) { +; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar2: +; CHECK-NOT: vmov +; CHECK: vcvtph2ps (% + + %load = load i64, i64* %ptr + %ins = insertelement <2 x i64> undef, i64 %load, i32 0 + %bc = bitcast <2 x i64> %ins to <8 x i16> + %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) + ret <4 x float> %res +} + define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind { entry: ; CHECK-LABEL: test_x86_vcvtps2ph_256_m: |
