[x86] regenerate checks with update_llc_test_checks.py

The dream of a unified check-line auto-generator for all phases of compilation is dead.
The llc script has already diverged to be better at its goal, so having 2 scripts that
do almost the same thing is just causing confusion.

We can rip out the llc ability in update_test_checks.py next and rename it, so it will
be clear that we have one script for llc check auto-generation and another for opt.

llvm-svn: 305206

28 files changed, 33 insertions, 160 deletions

diff --git a/llvm/test/CodeGen/X86/fp-select-cmp-and.ll b/llvm/test/CodeGen/X86/fp-select-cmp-and.ll
index e012809cf48..651d7a3351c 100644
--- a/llvm/test/CodeGen/X86/fp-select-cmp-and.ll
+++ b/llvm/test/CodeGen/X86/fp-select-cmp-and.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s
 
 define double @test1(double %a, double %b, double %eps) {
@@ -7,7 +7,6 @@ define double @test1(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    cmpltsd %xmm2, %xmm0
 ; CHECK-NEXT:    andpd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp olt double %a, %eps
   %cond = select i1 %cmp, double %b, double 0.000000e+00
   ret double %cond
@@ -19,7 +18,6 @@ define double @test2(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    cmplesd %xmm2, %xmm0
 ; CHECK-NEXT:    andpd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ole double %a, %eps
   %cond = select i1 %cmp, double %b, double 0.000000e+00
   ret double %cond
@@ -32,7 +30,6 @@ define double @test3(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    andpd %xmm1, %xmm2
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ogt double %a, %eps
   %cond = select i1 %cmp, double %b, double 0.000000e+00
   ret double %cond
@@ -45,7 +42,6 @@ define double @test4(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    andpd %xmm1, %xmm2
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge double %a, %eps
   %cond = select i1 %cmp, double %b, double 0.000000e+00
   ret double %cond
@@ -57,7 +53,6 @@ define double @test5(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    cmpltsd %xmm2, %xmm0
 ; CHECK-NEXT:    andnpd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp olt double %a, %eps
   %cond = select i1 %cmp, double 0.000000e+00, double %b
   ret double %cond
@@ -69,7 +64,6 @@ define double @test6(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    cmplesd %xmm2, %xmm0
 ; CHECK-NEXT:    andnpd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ole double %a, %eps
   %cond = select i1 %cmp, double 0.000000e+00, double %b
   ret double %cond
@@ -82,7 +76,6 @@ define double @test7(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    andnpd %xmm1, %xmm2
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ogt double %a, %eps
   %cond = select i1 %cmp, double 0.000000e+00, double %b
   ret double %cond
@@ -95,7 +88,6 @@ define double @test8(double %a, double %b, double %eps) {
 ; CHECK-NEXT:    andnpd %xmm1, %xmm2
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge double %a, %eps
   %cond = select i1 %cmp, double 0.000000e+00, double %b
   ret double %cond
@@ -107,7 +99,6 @@ define float @test9(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    cmpltss %xmm2, %xmm0
 ; CHECK-NEXT:    andps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp olt float %a, %eps
   %cond = select i1 %cmp, float %b, float 0.000000e+00
   ret float %cond
@@ -119,7 +110,6 @@ define float @test10(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    cmpless %xmm2, %xmm0
 ; CHECK-NEXT:    andps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ole float %a, %eps
   %cond = select i1 %cmp, float %b, float 0.000000e+00
   ret float %cond
@@ -132,7 +122,6 @@ define float @test11(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    andps %xmm1, %xmm2
 ; CHECK-NEXT:    movaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ogt float %a, %eps
   %cond = select i1 %cmp, float %b, float 0.000000e+00
   ret float %cond
@@ -145,7 +134,6 @@ define float @test12(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    andps %xmm1, %xmm2
 ; CHECK-NEXT:    movaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge float %a, %eps
   %cond = select i1 %cmp, float %b, float 0.000000e+00
   ret float %cond
@@ -157,7 +145,6 @@ define float @test13(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    cmpltss %xmm2, %xmm0
 ; CHECK-NEXT:    andnps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp olt float %a, %eps
   %cond = select i1 %cmp, float 0.000000e+00, float %b
   ret float %cond
@@ -169,7 +156,6 @@ define float @test14(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    cmpless %xmm2, %xmm0
 ; CHECK-NEXT:    andnps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ole float %a, %eps
   %cond = select i1 %cmp, float 0.000000e+00, float %b
   ret float %cond
@@ -182,7 +168,6 @@ define float @test15(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    andnps %xmm1, %xmm2
 ; CHECK-NEXT:    movaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp ogt float %a, %eps
   %cond = select i1 %cmp, float 0.000000e+00, float %b
   ret float %cond
@@ -195,7 +180,6 @@ define float @test16(float %a, float %b, float %eps) {
 ; CHECK-NEXT:    andnps %xmm1, %xmm2
 ; CHECK-NEXT:    movaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge float %a, %eps
   %cond = select i1 %cmp, float 0.000000e+00, float %b
   ret float %cond
@@ -210,7 +194,6 @@ define float @test17(float %a, float %b, float %c, float %eps) {
 ; CHECK-NEXT:    orps %xmm2, %xmm3
 ; CHECK-NEXT:    movaps %xmm3, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge float %a, %eps
   %cond = select i1 %cmp, float %c, float %b
   ret float %cond
@@ -225,7 +208,6 @@ define double @test18(double %a, double %b, double %c, double %eps) {
 ; CHECK-NEXT:    orpd %xmm2, %xmm3
 ; CHECK-NEXT:    movapd %xmm3, %xmm0
 ; CHECK-NEXT:    retq
-;
   %cmp = fcmp oge double %a, %eps
   %cond = select i1 %cmp, double %c, double %b
   ret double %cond
diff --git a/llvm/test/CodeGen/X86/immediate_merging64.ll b/llvm/test/CodeGen/X86/immediate_merging64.ll
index ea8ace12a86..4bc9d4af644 100644
--- a/llvm/test/CodeGen/X86/immediate_merging64.ll
+++ b/llvm/test/CodeGen/X86/immediate_merging64.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 ; Check that multiple instances of 64-bit constants encodable as
@@ -14,7 +14,6 @@ define i1 @imm_multiple_users(i64 %a, i64* %b) optsize {
 ; CHECK-NEXT:    cmpq %rax, %rdi
 ; CHECK-NEXT:    sete %al
 ; CHECK-NEXT:    retq
-;
   store i64 -1, i64* %b, align 8
   %cmp = icmp eq i64 %a, -1
   ret i1 %cmp
@@ -32,7 +31,6 @@ define void @memset_zero(i8* noalias nocapture %D) optsize {
 ; CHECK-NEXT:    movq %rax, 7(%rdi)
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %D, i8 0, i64 15, i32 1, i1 false)
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/loop-search.ll b/llvm/test/CodeGen/X86/loop-search.ll
index 6b29a726fc1..fda4ecec0e6 100644
--- a/llvm/test/CodeGen/X86/loop-search.ll
+++ b/llvm/test/CodeGen/X86/loop-search.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 ; This test comes from PR27136
@@ -35,7 +35,6 @@ define zeroext i1 @search(i32 %needle, i32* nocapture readonly %haystack, i32 %c
 ; CHECK-NEXT:    movb $1, %al
 ; CHECK-NEXT:    ## kill: %AL<def> %AL<kill> %EAX<kill>
 ; CHECK-NEXT:    retq
-;
 entry:
   %cmp5 = icmp sgt i32 %count, 0
   br i1 %cmp5, label %for.body.preheader, label %cleanup
diff --git a/llvm/test/CodeGen/X86/mask-negated-bool.ll b/llvm/test/CodeGen/X86/mask-negated-bool.ll
index c5c121c5296..779641cee7d 100644
--- a/llvm/test/CodeGen/X86/mask-negated-bool.ll
+++ b/llvm/test/CodeGen/X86/mask-negated-bool.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 define i32 @mask_negated_zext_bool1(i1 %x) {
@@ -7,7 +7,6 @@ define i32 @mask_negated_zext_bool1(i1 %x) {
 ; CHECK-NEXT:    andl $1, %edi
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
-;
   %ext = zext i1 %x to i32
   %neg = sub i32 0, %ext
   %and = and i32 %neg, 1
@@ -19,7 +18,6 @@ define i32 @mask_negated_zext_bool2(i1 zeroext %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    retq
-;
   %ext = zext i1 %x to i32
   %neg = sub i32 0, %ext
   %and = and i32 %neg, 1
@@ -31,7 +29,6 @@ define <4 x i32> @mask_negated_zext_bool_vec(<4 x i1> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
-;
   %ext = zext <4 x i1> %x to <4 x i32>
   %neg = sub <4 x i32> zeroinitializer, %ext
   %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1>
@@ -44,7 +41,6 @@ define i32 @mask_negated_sext_bool1(i1 %x) {
 ; CHECK-NEXT:    andl $1, %edi
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
-;
   %ext = sext i1 %x to i32
   %neg = sub i32 0, %ext
   %and = and i32 %neg, 1
@@ -56,7 +52,6 @@ define i32 @mask_negated_sext_bool2(i1 zeroext %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    retq
-;
   %ext = sext i1 %x to i32
   %neg = sub i32 0, %ext
   %and = and i32 %neg, 1
@@ -68,7 +63,6 @@ define <4 x i32> @mask_negated_sext_bool_vec(<4 x i1> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
-;
   %ext = sext <4 x i1> %x to <4 x i32>
   %neg = sub <4 x i32> zeroinitializer, %ext
   %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/X86/memset-2.ll b/llvm/test/CodeGen/X86/memset-2.ll
index a02ef29ca6b..1ac972048f1 100644
--- a/llvm/test/CodeGen/X86/memset-2.ll
+++ b/llvm/test/CodeGen/X86/memset-2.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=i386-apple-darwin9 -mcpu=yonah < %s | FileCheck %s
 
 define fastcc void @t1() nounwind {
@@ -10,7 +10,6 @@ define fastcc void @t1() nounwind {
 ; CHECK-NEXT:    pushl $0
 ; CHECK-NEXT:    calll _memset
 ; CHECK-NEXT:    addl $16, %esp
-;
 entry:
   call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false)
   unreachable
@@ -23,7 +22,6 @@ define fastcc void @t2(i8 signext %c) nounwind {
 ; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $76, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    calll _memset
-;
 entry:
   call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false)
   unreachable
@@ -40,7 +38,6 @@ define void @t3(i8* nocapture %s, i8 %a) nounwind {
 ; CHECK-NEXT:    movl %ecx, 4(%eax)
 ; CHECK-NEXT:    movl %ecx, (%eax)
 ; CHECK-NEXT:    retl
-;
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
   ret void
@@ -58,7 +55,6 @@ define void @t4(i8* nocapture %s, i8 %a) nounwind {
 ; CHECK-NEXT:    movw %cx, 12(%eax)
 ; CHECK-NEXT:    movb %cl, 14(%eax)
 ; CHECK-NEXT:    retl
-;
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
   ret void
diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll
index 769fe87880b..13258fd81de 100644
--- a/llvm/test/CodeGen/X86/memset-nonzero.ll
+++ b/llvm/test/CodeGen/X86/memset-nonzero.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse | FileCheck %s --check-prefix=SSE
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2 | FileCheck %s --check-prefix=SSE
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2,-slow-unaligned-mem-16 | FileCheck %s --check-prefix=SSE2FAST
@@ -26,7 +26,6 @@ define void @memset_16_nonzero_bytes(i8* %x) {
 ; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
 ; AVX-NEXT:    vmovups %xmm0, (%rdi)
 ; AVX-NEXT:    retq
-;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 16, i64 -1)
   ret void
 }
@@ -54,7 +53,6 @@ define void @memset_32_nonzero_bytes(i8* %x) {
 ; AVX-NEXT:    vmovups %ymm0, (%rdi)
 ; AVX-NEXT:    vzeroupper
 ; AVX-NEXT:    retq
-;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 32, i64 -1)
   ret void
 }
@@ -89,7 +87,6 @@ define void @memset_64_nonzero_bytes(i8* %x) {
 ; AVX-NEXT:    vmovups %ymm0, (%rdi)
 ; AVX-NEXT:    vzeroupper
 ; AVX-NEXT:    retq
-;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 64, i64 -1)
   ret void
 }
@@ -138,7 +135,6 @@ define void @memset_128_nonzero_bytes(i8* %x) {
 ; AVX-NEXT:    vmovups %ymm0, (%rdi)
 ; AVX-NEXT:    vzeroupper
 ; AVX-NEXT:    retq
-;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1)
   ret void
 }
@@ -189,7 +185,6 @@ define void @memset_256_nonzero_bytes(i8* %x) {
 ; AVX-NEXT:    vmovups %ymm0, (%rdi)
 ; AVX-NEXT:    vzeroupper
 ; AVX-NEXT:    retq
-;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 256, i64 -1)
   ret void
 }
@@ -231,7 +226,6 @@ define void @memset_16_nonconst_bytes(i8* %x, i8 %c) {
 ; AVX2-NEXT:    vpbroadcastb %xmm0, %xmm0
 ; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 16, i32 1, i1 false)
   ret void
 }
@@ -275,7 +269,6 @@ define void @memset_32_nonconst_bytes(i8* %x, i8 %c) {
 ; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 32, i32 1, i1 false)
   ret void
 }
@@ -327,7 +320,6 @@ define void @memset_64_nonconst_bytes(i8* %x, i8 %c) {
 ; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 64, i32 1, i1 false)
   ret void
 }
@@ -395,7 +387,6 @@ define void @memset_128_nonconst_bytes(i8* %x, i8 %c) {
 ; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 128, i32 1, i1 false)
   ret void
 }
@@ -461,7 +452,6 @@ define void @memset_256_nonconst_bytes(i8* %x, i8 %c) {
 ; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-;
   tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 256, i32 1, i1 false)
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/memset64-on-x86-32.ll b/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
index 861cb88b0f5..a7a3c61b139 100644
--- a/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
+++ b/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-unknown   -mattr=sse4.2 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown   -mattr=ssse3   | FileCheck %s --check-prefix=SLOW_32
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=ssse3   | FileCheck %s --check-prefix=SLOW_64
@@ -51,7 +51,6 @@ define void @bork() nounwind {
 ; SLOW_64-NEXT:    movq $0, 8
 ; SLOW_64-NEXT:    movq $0, 0
 ; SLOW_64-NEXT:    retq
-;
   call void @llvm.memset.p0i8.i64(i8* null, i8 0, i64 80, i32 4, i1 false)
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/negate-i1.ll b/llvm/test/CodeGen/X86/negate-i1.ll
index f1678a1b22f..13f831fd37b 100644
--- a/llvm/test/CodeGen/X86/negate-i1.ll
+++ b/llvm/test/CodeGen/X86/negate-i1.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=i386-unknown-unknown   | FileCheck %s --check-prefix=X32
 
@@ -16,7 +16,6 @@ define i8 @select_i8_neg1_or_0(i1 %a) {
 ; X32-NEXT:    andb $1, %al
 ; X32-NEXT:    negb %al
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i8
   ret i8 %b
 }
@@ -33,7 +32,6 @@ define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    negb %al
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i8
   ret i8 %b
 }
@@ -53,7 +51,6 @@ define i16 @select_i16_neg1_or_0(i1 %a) {
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i16
   ret i16 %b
 }
@@ -72,7 +69,6 @@ define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i16
   ret i16 %b
 }
@@ -91,7 +87,6 @@ define i32 @select_i32_neg1_or_0(i1 %a) {
 ; X32-NEXT:    andl $1, %eax
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i32
   ret i32 %b
 }
@@ -108,7 +103,6 @@ define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i32
   ret i32 %b
 }
@@ -129,7 +123,6 @@ define i64 @select_i64_neg1_or_0(i1 %a) {
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i64
   ret i64 %b
 }
@@ -147,7 +140,6 @@ define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X32-NEXT:    negl %eax
 ; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    retl
-;
   %b = sext i1 %a to i64
   ret i64 %b
 }
diff --git a/llvm/test/CodeGen/X86/negate-shift.ll b/llvm/test/CodeGen/X86/negate-shift.ll
index 54ffc8e71e0..cbe2f9456fa 100644
--- a/llvm/test/CodeGen/X86/negate-shift.ll
+++ b/llvm/test/CodeGen/X86/negate-shift.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
 
 define i32 @neg_lshr_signbit(i32 %x) {
@@ -7,7 +7,6 @@ define i32 @neg_lshr_signbit(i32 %x) {
 ; X64-NEXT:    sarl $31, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
-;
   %sh = lshr i32 %x, 31
   %neg = sub i32 0, %sh
   ret i32 %neg
@@ -19,7 +18,6 @@ define i64 @neg_ashr_signbit(i64 %x) {
 ; X64-NEXT:    shrq $63, %rdi
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    retq
-;
   %sh = ashr i64 %x, 63
   %neg = sub i64 0, %sh
   ret i64 %neg
@@ -30,7 +28,6 @@ define <4 x i32> @neg_ashr_signbit_vec(<4 x i32> %x) {
 ; X64:       # BB#0:
 ; X64-NEXT:    psrld $31, %xmm0
 ; X64-NEXT:    retq
-;
   %sh = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %neg = sub <4 x i32> zeroinitializer, %sh
   ret <4 x i32> %neg
@@ -41,7 +38,6 @@ define <8 x i16> @neg_lshr_signbit_vec(<8 x i16> %x) {
 ; X64:       # BB#0:
 ; X64-NEXT:    psraw $15, %xmm0
 ; X64-NEXT:    retq
-;
   %sh = lshr <8 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
   %neg = sub <8 x i16> zeroinitializer, %sh
   ret <8 x i16> %neg
diff --git a/llvm/test/CodeGen/X86/negate.ll b/llvm/test/CodeGen/X86/negate.ll
index 6f07378e0e4..5bdb11479af 100644
--- a/llvm/test/CodeGen/X86/negate.ll
+++ b/llvm/test/CodeGen/X86/negate.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 define i32 @negate_nuw(i32 %x) {
@@ -6,7 +6,6 @@ define i32 @negate_nuw(i32 %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
-;
   %neg = sub nuw i32 0, %x
   ret i32 %neg
 }
@@ -16,7 +15,6 @@ define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %neg = sub nuw <4 x i32> zeroinitializer, %x
   ret <4 x i32> %neg
 }
@@ -26,7 +24,6 @@ define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
-;
   %signbit = and i8 %x, 128
   %neg = sub nsw i8 0, %signbit
   ret i8 %neg
@@ -37,7 +34,6 @@ define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %neg = sub nsw <4 x i32> zeroinitializer, %signbit
   ret <4 x i32> %neg
@@ -49,7 +45,6 @@ define i8 @negate_zero_or_minsigned(i8 %x) {
 ; CHECK-NEXT:    shlb $7, %dil
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
-;
   %signbit = shl i8 %x, 7
   %neg = sub i8 0, %signbit
   ret i8 %neg
@@ -60,7 +55,6 @@ define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
-;
   %signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
   %neg = sub <4 x i32> zeroinitializer, %signbit
   ret <4 x i32> %neg
diff --git a/llvm/test/CodeGen/X86/negative-sin.ll b/llvm/test/CodeGen/X86/negative-sin.ll
index bc38021b562..94369e3e8d0 100644
--- a/llvm/test/CodeGen/X86/negative-sin.ll
+++ b/llvm/test/CodeGen/X86/negative-sin.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
 
 declare double @sin(double %f)
@@ -16,7 +16,6 @@ define double @strict(double %e) nounwind {
 ; CHECK-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
   %f = fsub double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub double 0.0, %g
@@ -29,8 +28,7 @@ define double @strict(double %e) nounwind {
 define double @fast(double %e) nounwind {
 ; CHECK-LABEL: fast:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    jmp sin
-;
+; CHECK-NEXT:    jmp sin # TAILCALL
   %f = fsub fast double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub fast double 0.0, %g
@@ -42,8 +40,7 @@ define double @fast(double %e) nounwind {
 define double @nsz(double %e) nounwind {
 ; CHECK-LABEL: nsz:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    jmp sin
-;
+; CHECK-NEXT:    jmp sin # TAILCALL
   %f = fsub nsz double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub nsz double 0.0, %g
@@ -62,7 +59,6 @@ define double @semi_strict1(double %e) nounwind {
 ; CHECK-NEXT:    vxorpd {{.*}}(%rip), %xmm0, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
   %f = fsub double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub nsz double 0.0, %g
@@ -80,7 +76,6 @@ define double @semi_strict2(double %e) nounwind {
 ; CHECK-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
   %f = fsub nsz double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub double 0.0, %g
@@ -93,8 +88,7 @@ define double @semi_strict2(double %e) nounwind {
 define double @fn_attr(double %e) nounwind #0 {
 ; CHECK-LABEL: fn_attr:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    jmp sin
-;
+; CHECK-NEXT:    jmp sin # TAILCALL
   %f = fsub double 0.0, %e
   %g = call double @sin(double %f) readonly
   %h = fsub double 0.0, %g
diff --git a/llvm/test/CodeGen/X86/no-sse2-avg.ll b/llvm/test/CodeGen/X86/no-sse2-avg.ll
index 0ed0a7f74cb..e4b97c17047 100644
--- a/llvm/test/CodeGen/X86/no-sse2-avg.ll
+++ b/llvm/test/CodeGen/X86/no-sse2-avg.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s
 
@@ -23,7 +23,6 @@ define <16 x i8> @PR27973() {
 ; CHECK-NEXT:    movb $0, (%rdi)
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
-;
   %t0 = zext <16 x i8> zeroinitializer to <16 x i32>
   %t1 = add nuw nsw <16 x i32> %t0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %t2 = lshr <16 x i32> %t1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/X86/not-and-simplify.ll b/llvm/test/CodeGen/X86/not-and-simplify.ll
index 83b2be83d55..87aa10a6e29 100644
--- a/llvm/test/CodeGen/X86/not-and-simplify.ll
+++ b/llvm/test/CodeGen/X86/not-and-simplify.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-bmi | FileCheck %s --check-prefix=ALL --check-prefix=NO_BMI
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=ALL --check-prefix=BMI
 
diff --git a/llvm/test/CodeGen/X86/pr13577.ll b/llvm/test/CodeGen/X86/pr13577.ll
index 1b1622513ea..665df2c183b 100644
--- a/llvm/test/CodeGen/X86/pr13577.ll
+++ b/llvm/test/CodeGen/X86/pr13577.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-darwin | FileCheck %s
 
 ; CHECK-LABEL: LCPI0_0:
@@ -12,12 +12,11 @@ define x86_fp80 @foo(x86_fp80 %a) {
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fstpt -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    testb $-128, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    flds LCPI0_0(%rip)
-; CHECK-NEXT:    flds LCPI0_1(%rip)
+; CHECK-NEXT:    flds {{.*}}(%rip)
+; CHECK-NEXT:    flds {{.*}}(%rip)
 ; CHECK-NEXT:    fcmovne %st(1), %st(0)
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    retq
-;
   %1 = tail call x86_fp80 @copysignl(x86_fp80 0xK7FFF8000000000000000, x86_fp80 %a) nounwind readnone
   ret x86_fp80 %1
 }
@@ -34,7 +33,6 @@ define float @pr26070() {
 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
-;
   %c = call float @copysignf(float 1.0, float undef) readnone
   ret float %c
 }
diff --git a/llvm/test/CodeGen/X86/pr18014.ll b/llvm/test/CodeGen/X86/pr18014.ll
index bb3b9c23f1e..cba065002d5 100644
--- a/llvm/test/CodeGen/X86/pr18014.ll
+++ b/llvm/test/CodeGen/X86/pr18014.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s
 
 ; Ensure PSRAD is generated as the condition is consumed by both PADD and
@@ -14,7 +14,6 @@ define <4 x i32> @foo(<4 x i32>* %p, <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v
 ; CHECK-NEXT:    movaps %xmm2, (%rdi)
 ; CHECK-NEXT:    movdqa %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %sext_cond = sext <4 x i1> %cond to <4 x i32>
   %t1 = add <4 x i32> %v1, %sext_cond
   %t2 = select <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v2
diff --git a/llvm/test/CodeGen/X86/rem.ll b/llvm/test/CodeGen/X86/rem.ll
index cc591e5ac00..7b138f02eb4 100644
--- a/llvm/test/CodeGen/X86/rem.ll
+++ b/llvm/test/CodeGen/X86/rem.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
 
 define i32 @test1(i32 %X) {
@@ -19,7 +19,6 @@ define i32 @test1(i32 %X) {
 ; CHECK-NEXT:    subl %eax, %ecx
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    retl
-;
   %tmp1 = srem i32 %X, 255
   ret i32 %tmp1
 }
@@ -35,7 +34,6 @@ define i32 @test2(i32 %X) {
 ; CHECK-NEXT:    andl $-256, %ecx
 ; CHECK-NEXT:    subl %ecx, %eax
 ; CHECK-NEXT:    retl
-;
   %tmp1 = srem i32 %X, 256
   ret i32 %tmp1
 }
@@ -54,7 +52,6 @@ define i32 @test3(i32 %X) {
 ; CHECK-NEXT:    subl %eax, %ecx
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    retl
-;
   %tmp1 = urem i32 %X, 255
   ret i32 %tmp1
 }
@@ -64,7 +61,6 @@ define i32 @test4(i32 %X) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    retl
-;
   %tmp1 = urem i32 %X, 256
   ret i32 %tmp1
 }
@@ -77,8 +73,8 @@ define i32 @test5(i32 %X) nounwind readnone {
 ; CHECK-NEXT:    idivl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl %edx, %eax
 ; CHECK-NEXT:    retl
-;
 entry:
   %0 = srem i32 41, %X
   ret i32 %0
 }
+
diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll
index 213ca95fc78..66ad8c3f40f 100644
--- a/llvm/test/CodeGen/X86/sar_fold64.ll
+++ b/llvm/test/CodeGen/X86/sar_fold64.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 define i32 @shl48sar47(i64 %a) #0 {
@@ -8,7 +8,6 @@ define i32 @shl48sar47(i64 %a) #0 {
 ; CHECK-NEXT:    addl %eax, %eax
 ; CHECK-NEXT:    # kill: %EAX<def> %EAX<kill> %RAX<kill>
 ; CHECK-NEXT:    retq
-;
   %1 = shl i64 %a, 48
   %2 = ashr exact i64 %1, 47
   %3 = trunc i64 %2 to i32
@@ -22,7 +21,6 @@ define i32 @shl48sar49(i64 %a) #0 {
 ; CHECK-NEXT:    shrq %rax
 ; CHECK-NEXT:    # kill: %EAX<def> %EAX<kill> %RAX<kill>
 ; CHECK-NEXT:    retq
-;
   %1 = shl i64 %a, 48
   %2 = ashr exact i64 %1, 49
   %3 = trunc i64 %2 to i32
@@ -36,7 +34,6 @@ define i32 @shl56sar55(i64 %a) #0 {
 ; CHECK-NEXT:    addl %eax, %eax
 ; CHECK-NEXT:    # kill: %EAX<def> %EAX<kill> %RAX<kill>
 ; CHECK-NEXT:    retq
-;
   %1 = shl i64 %a, 56
   %2 = ashr exact i64 %1, 55
   %3 = trunc i64 %2 to i32
@@ -50,7 +47,6 @@ define i32 @shl56sar57(i64 %a) #0 {
 ; CHECK-NEXT:    shrq %rax
 ; CHECK-NEXT:    # kill: %EAX<def> %EAX<kill> %RAX<kill>
 ; CHECK-NEXT:    retq
-;
   %1 = shl i64 %a, 56
   %2 = ashr exact i64 %1, 57
   %3 = trunc i64 %2 to i32
@@ -64,7 +60,6 @@ define i8 @all_sign_bit_ashr(i8 %x) {
 ; CHECK-NEXT:    negb %dil
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
-;
   %and = and i8 %x, 1
   %neg = sub i8 0, %and
   %sar = ashr i8 %neg, 6
@@ -79,7 +74,6 @@ define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) {
 ; CHECK-NEXT:    psubd %xmm0, %xmm1
 ; CHECK-NEXT:    movdqa %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
   %neg = sub <4 x i32> zeroinitializer, %and
   %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0>
diff --git a/llvm/test/CodeGen/X86/select-with-and-or.ll b/llvm/test/CodeGen/X86/select-with-and-or.ll
index f49da8576d1..45e4384d0fa 100644
--- a/llvm/test/CodeGen/X86/select-with-and-or.ll
+++ b/llvm/test/CodeGen/X86/select-with-and-or.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
@@ -7,7 +7,6 @@ define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK-NEXT:    vcmpnleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vandps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer
   ret <4 x i32> %r
@@ -19,7 +18,6 @@ define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK-NEXT:    vcmpnleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vorps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c
   ret <4 x i32> %r
@@ -31,7 +29,6 @@ define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK-NEXT:    vcmpleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vandps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c
   ret <4 x i32> %r
@@ -43,7 +40,6 @@ define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK-NEXT:    vcmpleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vorps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %r
@@ -54,7 +50,6 @@ define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vcmpnleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %r = sext <4 x i1> %f to <4 x i32>
   ret <4 x i32> %r
@@ -65,7 +60,6 @@ define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vcmpleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %not.f = fcmp oge <4 x float> %a, %b
   %r = sext <4 x i1> %not.f to <4 x i32>
   ret <4 x i32> %r
@@ -77,7 +71,6 @@ define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) {
 ; CHECK-NEXT:    vcmpnleps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vandps (%rdi), %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ult <4 x float> %a, %b
   %l = load <4 x i32>, <4 x i32>* %p, align 16
   %r = select <4 x i1> %f, <4 x i32> %l, <4 x i32> zeroinitializer
@@ -92,7 +85,6 @@ define <2 x double> @test1f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK-NEXT:    vcmpltpd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vandpd %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ogt <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> %c, <2 x double> zeroinitializer
   ret <2 x double> %r
@@ -104,7 +96,6 @@ define <2 x double> @test2f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK-NEXT:    vcmplepd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vorpd %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp oge <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> %c
   ret <2 x double> %r
@@ -116,7 +107,6 @@ define <2 x double> @test3f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK-NEXT:    vcmpnltpd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vandpd %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp olt <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> %c
   ret <2 x double> %r
@@ -128,7 +118,6 @@ define <2 x double> @test4f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK-NEXT:    vcmpnlepd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vorpd %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ole <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> %c, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>
   ret <2 x double> %r
@@ -139,7 +128,6 @@ define <2 x double> @test5f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vcmpnlepd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ugt <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> zeroinitializer
   ret <2 x double> %r
@@ -150,7 +138,6 @@ define <2 x double> @test6f(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vcmpltpd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp ule <2 x double> %a, %b
   %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>
   ret <2 x double> %r
@@ -162,7 +149,6 @@ define <2 x double> @test7f(<2 x double> %a, <2 x double> %b, <2 x double>* %p)
 ; CHECK-NEXT:    vcmpeqpd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vandpd (%rdi), %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %f = fcmp oeq <2 x double> %a, %b
   %l = load <2 x double>, <2 x double>* %p, align 16
   %r = select <2 x i1> %f, <2 x double> %l, <2 x double> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/sext-setcc-self.ll b/llvm/test/CodeGen/X86/sext-setcc-self.ll
index e739d21e64e..9cbd3d85b38 100644
--- a/llvm/test/CodeGen/X86/sext-setcc-self.ll
+++ b/llvm/test/CodeGen/X86/sext-setcc-self.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 
 define <4 x i32> @test_ueq(<4 x float> %in) {
@@ -6,7 +6,6 @@ define <4 x i32> @test_ueq(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp ueq <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
@@ -17,7 +16,6 @@ define <4 x i32> @test_uge(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp uge <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
@@ -28,7 +26,6 @@ define <4 x i32> @test_ule(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp ule <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
@@ -39,7 +36,6 @@ define <4 x i32> @test_one(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp one <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
@@ -50,7 +46,6 @@ define <4 x i32> @test_ogt(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp ogt <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
@@ -61,7 +56,6 @@ define <4 x i32> @test_olt(<4 x float> %in) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-;
   %t0 = fcmp olt <4 x float> %in, %in
   %t1 = sext <4 x i1> %t0 to <4 x i32>
   ret <4 x i32> %t1
diff --git a/llvm/test/CodeGen/X86/shift-pcmp.ll b/llvm/test/CodeGen/X86/shift-pcmp.ll
index adfd2f143d1..f509da2674b 100644
--- a/llvm/test/CodeGen/X86/shift-pcmp.ll
+++ b/llvm/test/CodeGen/X86/shift-pcmp.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
 ; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
 
@@ -14,7 +14,6 @@ define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) {
 ; AVX-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-;
   %icmp = icmp eq <8 x i16> %a, %b
   %zext = zext <8 x i1> %icmp to <8 x i16>
   %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
@@ -34,7 +33,6 @@ define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
 ; AVX-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-;
   %icmp = icmp eq <8 x i16> %a, %b
   %zext = zext <8 x i1> %icmp to <8 x i16>
   %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 undef, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
diff --git a/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
index 77497d38c89..2ecba887f7c 100644
--- a/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
 
 define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
diff --git a/llvm/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll
index 26af37e3029..9bda90a2302 100644
--- a/llvm/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse4.1 | FileCheck %s
 
 ; This test works just like the non-upgrade one except that it only checks
@@ -230,7 +230,6 @@ define <16 x i8> @max_epi8(<16 x i8> %a0, <16 x i8> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pmaxsb %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1)
   ret <16 x i8> %res
 }
@@ -241,7 +240,6 @@ define <16 x i8> @min_epi8(<16 x i8> %a0, <16 x i8> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pminsb %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1)
   ret <16 x i8> %res
 }
@@ -252,7 +250,6 @@ define <8 x i16> @max_epu16(<8 x i16> %a0, <8 x i16> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pmaxuw %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1)
   ret <8 x i16> %res
 }
@@ -263,7 +260,6 @@ define <8 x i16> @min_epu16(<8 x i16> %a0, <8 x i16> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pminuw %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1)
   ret <8 x i16> %res
 }
@@ -274,7 +270,6 @@ define <4 x i32> @max_epi32(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pmaxsd %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1)
   ret <4 x i32> %res
 }
@@ -285,7 +280,6 @@ define <4 x i32> @min_epi32(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pminsd %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1)
   ret <4 x i32> %res
 }
@@ -296,7 +290,6 @@ define <4 x i32> @max_epu32(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pmaxud %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1)
   ret <4 x i32> %res
 }
@@ -307,7 +300,6 @@ define <4 x i32> @min_epu32(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pminud %xmm1, %xmm0
 ; CHECK-NEXT:    retl
-;
   %res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1)
   ret <4 x i32> %res
 }
diff --git a/llvm/test/CodeGen/X86/statepoint-live-in.ll b/llvm/test/CodeGen/X86/statepoint-live-in.ll
index aaa4d7c8422..0179d37ad4e 100644
--- a/llvm/test/CodeGen/X86/statepoint-live-in.ll
+++ b/llvm/test/CodeGen/X86/statepoint-live-in.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
@@ -16,7 +16,6 @@ define void @test1(i32 %a) gc "statepoint-example" {
 ; CHECK-NEXT:  Ltmp0:
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
 entry:
 ; We expect the argument to be passed in an extra register to bar
   %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
@@ -49,7 +48,6 @@ define void @test2(i32 %a, i32 %b) gc "statepoint-example" {
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    popq %rbp
 ; CHECK-NEXT:    retq
-;
 entry:
 ; Because the first call clobbers esi, we have to move the values into
 ; new registers.  Note that they stay in the registers for both calls.
@@ -68,7 +66,6 @@ define void @test3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %
 ; CHECK-NEXT:  Ltmp3:
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
 entry:
 ; We directly reference the argument slot
   %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 9, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i)
@@ -89,7 +86,6 @@ define void @test4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %
 ; CHECK-NEXT:  Ltmp4:
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
-;
 entry:
   %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 26, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z)
   ret void
@@ -111,7 +107,6 @@ define  i32 addrspace(1)* @test5(i32 %a, i32 addrspace(1)* %p) gc "statepoint-ex
 ; CHECK-NEXT:    movq (%rsp), %rax
 ; CHECK-NEXT:    popq %rcx
 ; CHECK-NEXT:    retq
-;
 entry:
   %token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a, i32 addrspace(1)* %p, i32 addrspace(1)* %p)
   %p2 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token,  i32 9, i32 9)
@@ -139,7 +134,6 @@ define void @test6(i32 %a) gc "statepoint-example" {
 ; CHECK-NEXT:    addq $16, %rsp
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
 entry:
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a)
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
diff --git a/llvm/test/CodeGen/X86/urem-i8-constant.ll b/llvm/test/CodeGen/X86/urem-i8-constant.ll
index 45717f985c2..2a659b20de8 100644
--- a/llvm/test/CodeGen/X86/urem-i8-constant.ll
+++ b/llvm/test/CodeGen/X86/urem-i8-constant.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
 
 define i8 @foo(i8 %tmp325) {
@@ -14,7 +14,6 @@ define i8 @foo(i8 %tmp325) {
 ; CHECK-NEXT:    subb %al, %cl
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    retl
-;
   %t546 = urem i8 %tmp325, 37
   ret i8 %t546
 }
diff --git a/llvm/test/CodeGen/X86/urem-power-of-two.ll b/llvm/test/CodeGen/X86/urem-power-of-two.ll
index 469c573443e..1b56c87aad5 100644
--- a/llvm/test/CodeGen/X86/urem-power-of-two.ll
+++ b/llvm/test/CodeGen/X86/urem-power-of-two.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 ; The easy case: a constant power-of-2 divisor.
@@ -9,7 +9,6 @@ define i64 @const_pow_2(i64 %x) {
 ; CHECK-NEXT:    andl $31, %edi
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
-;
   %urem = urem i64 %x, 32
   ret i64 %urem
 }
@@ -25,7 +24,6 @@ define i25 @shift_left_pow_2(i25 %x, i25 %y) {
 ; CHECK-NEXT:    addl $33554431, %eax # imm = 0x1FFFFFF
 ; CHECK-NEXT:    andl %edi, %eax
 ; CHECK-NEXT:    retq
-;
   %shl = shl i25 1, %y
   %urem = urem i25 %x, %shl
   ret i25 %urem
@@ -43,7 +41,6 @@ define i16 @shift_right_pow_2(i16 %x, i16 %y) {
 ; CHECK-NEXT:    andl %edi, %eax
 ; CHECK-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; CHECK-NEXT:    retq
-;
   %shr = lshr i16 -32768, %y
   %urem = urem i16 %x, %shr
   ret i16 %urem
@@ -61,7 +58,6 @@ define i8 @and_pow_2(i8 %x, i8 %y) {
 ; CHECK-NEXT:    movzbl %ah, %eax # NOREX
 ; CHECK-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; CHECK-NEXT:    retq
-;
   %and = and i8 %y, 4
   %urem = urem i8 %x, %and
   ret i8 %urem
@@ -74,7 +70,6 @@ define <4 x i32> @vec_const_pow_2(<4 x i32> %x) {
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
-;
   %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
   ret <4 x i32> %urem
 }
diff --git a/llvm/test/CodeGen/X86/vec3.ll b/llvm/test/CodeGen/X86/vec3.ll
index 8eaf9f4f48e..e9c47ffd21c 100644
--- a/llvm/test/CodeGen/X86/vec3.ll
+++ b/llvm/test/CodeGen/X86/vec3.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse | FileCheck %s
 
 define <3 x float> @fadd(<3 x float> %v, float %d) {
@@ -7,7 +7,6 @@ define <3 x float> @fadd(<3 x float> %v, float %d) {
 ; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0,0,3]
 ; CHECK-NEXT:    addps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %ins = insertelement <3 x float> undef, float %d, i32 0
   %splat = shufflevector <3 x float> %ins, <3 x float> undef, <3 x i32> zeroinitializer
   %add = fadd <3 x float> %splat, %v
@@ -23,7 +22,6 @@ define <3 x float> @fdiv(<3 x float> %v, float %d) {
 ; CHECK-NEXT:    divps %xmm0, %xmm1
 ; CHECK-NEXT:    movaps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
-;
   %ins = insertelement <3 x float> undef, float %d, i32 0
   %splat = shufflevector <3 x float> %ins, <3 x float> undef, <3 x i32> zeroinitializer
   %div = fdiv <3 x float> %splat, %v
diff --git a/llvm/test/CodeGen/X86/vector-compare-combines.ll b/llvm/test/CodeGen/X86/vector-compare-combines.ll
index c25474d92f9..bd7cbfb4bac 100644
--- a/llvm/test/CodeGen/X86/vector-compare-combines.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-combines.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 
@@ -17,7 +17,6 @@ define <4 x i32> @PR27924_cmpeq(<4 x i32> %a, <4 x i32> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
-;
   %cmp = icmp sgt <4 x i32> %a, %b
   %max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b
   %sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b)
@@ -36,7 +35,6 @@ define <4 x i32> @PR27924_cmpgt(<4 x i32> %a, <4 x i32> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
-;
   %cmp = icmp sgt <4 x i32> %a, %b
   %max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b
   %sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b)
diff --git a/llvm/test/CodeGen/X86/vzero-excess.ll b/llvm/test/CodeGen/X86/vzero-excess.ll
index 0ed90741b61..9ddafec6518 100644
--- a/llvm/test/CodeGen/X86/vzero-excess.ll
+++ b/llvm/test/CodeGen/X86/vzero-excess.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 ; In the following 4 tests, the existing call to VZU/VZA ensures clean state before