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| author | Thomas Lively <tlively@google.com> | 2018-09-13 02:50:56 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2018-09-13 02:50:56 +0000 |
| commit | 56b34f6c51c8bee65cefd0bfb35b2a294032d6a3 (patch) | |
| tree | fc503d31a6be22ad03e366cc35e1906d47c6b6b5 | |
| parent | 08ebf19e5283ac666faecf7a0674f4d26a0c85e6 (diff) | |
| download | bcm5719-llvm-56b34f6c51c8bee65cefd0bfb35b2a294032d6a3.tar.gz bcm5719-llvm-56b34f6c51c8bee65cefd0bfb35b2a294032d6a3.zip | |
[WebAssembly] Add missing SIMD instruction attributes
Summary:
These attributes are copied from equivalent instructions in
WebAssemblyInstrInfo.td.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51518
llvm-svn: 342104
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 9f41ec3d3a6..6bda0cbd938 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -19,13 +19,14 @@ foreach SIZE = [2, 4, 8, 16, 32] in def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { + let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, [(set V128:$dst, (vec_t pat))], "v128.const\t$dst, "#args, "v128.const\t"#args, 0>; } multiclass SIMDLoad<ValueType vec_t> { - let mayLoad = 1 in + let mayLoad = 1, isAsCheapAsAMove = 1 in defm LOAD_#vec_t : SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr), (outs), (ins P2Align:$align, offset32_op:$off), [], @@ -33,7 +34,7 @@ multiclass SIMDLoad<ValueType vec_t> { "v128.load\t$off$align", 1>; } multiclass SIMDStore<ValueType vec_t> { - let mayStore = 1 in + let mayStore = 1, isAsCheapAsAMove = 1 in defm STORE_#vec_t : SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec), (outs), (ins P2Align:$align, offset32_op:$off), [], |
