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-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 9f41ec3d3a6..6bda0cbd938 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -19,13 +19,14 @@ foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
+ let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
[(set V128:$dst, (vec_t pat))],
"v128.const\t$dst, "#args,
"v128.const\t"#args, 0>;
}
multiclass SIMDLoad<ValueType vec_t> {
- let mayLoad = 1 in
+ let mayLoad = 1, isAsCheapAsAMove = 1 in
defm LOAD_#vec_t :
SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
(outs), (ins P2Align:$align, offset32_op:$off), [],
@@ -33,7 +34,7 @@ multiclass SIMDLoad<ValueType vec_t> {
"v128.load\t$off$align", 1>;
}
multiclass SIMDStore<ValueType vec_t> {
- let mayStore = 1 in
+ let mayStore = 1, isAsCheapAsAMove = 1 in
defm STORE_#vec_t :
SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
(outs), (ins P2Align:$align, offset32_op:$off), [],
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