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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-10-02 18:58:33 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-10-02 18:58:33 +0000
commit3d3b4d0c2c3d239ce2524349f47678e22f220db0 (patch)
treed668d085481e305c63fd8f7756f1023f34fbd019
parent7d910f2b115eded4212e2d67e9265c1a929c2000 (diff)
downloadbcm5719-llvm-3d3b4d0c2c3d239ce2524349f47678e22f220db0.tar.gz
bcm5719-llvm-3d3b4d0c2c3d239ce2524349f47678e22f220db0.zip
Add way to test for generic TargetOpcodes
The alternative would be to add a bit to the target's InstrFlags but that seems like a waste of a bit. llvm-svn: 249169
-rw-r--r--llvm/include/llvm/Target/TargetInstrInfo.h4
-rw-r--r--llvm/include/llvm/Target/TargetOpcodes.h4
2 files changed, 8 insertions, 0 deletions
diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h
index b9f85a133a3..0a35d4178d9 100644
--- a/llvm/include/llvm/Target/TargetInstrInfo.h
+++ b/llvm/include/llvm/Target/TargetInstrInfo.h
@@ -62,6 +62,10 @@ public:
virtual ~TargetInstrInfo();
+ static bool isGenericOpcode(unsigned Opc) {
+ return Opc <= TargetOpcode::GENERIC_OP_END;
+ }
+
/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
diff --git a/llvm/include/llvm/Target/TargetOpcodes.h b/llvm/include/llvm/Target/TargetOpcodes.h
index a7e2aa82a28..db37bdb6258 100644
--- a/llvm/include/llvm/Target/TargetOpcodes.h
+++ b/llvm/include/llvm/Target/TargetOpcodes.h
@@ -128,6 +128,10 @@ enum {
/// "zero cost" null checks in managed languages by allowing LLVM to fold
/// comparisons into existing memory operations.
FAULTING_LOAD_OP = 22,
+
+ /// BUILTIN_OP_END - This must be the last enum value in this list.
+ /// The target-specific post-isel opcode values start here.
+ GENERIC_OP_END = FAULTING_LOAD_OP,
};
} // end namespace TargetOpcode
} // end namespace llvm
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