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| author | Craig Topper <craig.topper@intel.com> | 2017-07-20 19:29:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-07-20 19:29:58 +0000 |
| commit | 27c12e088ee520c2416d30fcb292d6666377c01f (patch) | |
| tree | af7146b10f431e7c8808a15eb34c0a8e8a38a76d | |
| parent | 02959b3d054cd25a8d155df6345891693b25a618 (diff) | |
| download | bcm5719-llvm-27c12e088ee520c2416d30fcb292d6666377c01f.tar.gz bcm5719-llvm-27c12e088ee520c2416d30fcb292d6666377c01f.zip | |
[X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.
llvm-svn: 308657
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrCompiler.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/shift-and.ll | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 9d188d3d5e5..3547c6526f1 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1654,7 +1654,7 @@ multiclass MaskedShiftAmountPats<SDNode frag, string name> { // (shift x (and y, 63)) ==> (shift x, y) def : Pat<(frag GR64:$src1, (and CL, immShift64)), (!cast<Instruction>(name # "64rCL") GR64:$src1)>; - def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), + def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst), (!cast<Instruction>(name # "64mCL") addr:$dst)>; } diff --git a/llvm/test/CodeGen/X86/shift-and.ll b/llvm/test/CodeGen/X86/shift-and.ll index bb8eaa3c1cb..c61bff72ca6 100644 --- a/llvm/test/CodeGen/X86/shift-and.ll +++ b/llvm/test/CodeGen/X86/shift-and.ll @@ -99,7 +99,6 @@ define i64 @t5(i64 %t, i64 %val) nounwind { define void @t5ptr(i64 %t, i64* %ptr) nounwind { ; X64-LABEL: t5ptr: ; X64: ## BB#0: -; X64-NEXT: andb $-65, %dil ; X64-NEXT: movl %edi, %ecx ; X64-NEXT: shrq %cl, (%rsi) ; X64-NEXT: retq |
