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| author | Craig Topper <craig.topper@intel.com> | 2017-07-20 19:29:56 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-07-20 19:29:56 +0000 |
| commit | 02959b3d054cd25a8d155df6345891693b25a618 (patch) | |
| tree | 4987e6f3031bdc14156d770c62156c58b5021618 | |
| parent | e9f0c1e03160b9bceaf061370c050f05425278ee (diff) | |
| download | bcm5719-llvm-02959b3d054cd25a8d155df6345891693b25a618.tar.gz bcm5719-llvm-02959b3d054cd25a8d155df6345891693b25a618.zip | |
[X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form.
We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w
I'm assuming this was a mistake made back in r148024.
llvm-svn: 308656
| -rw-r--r-- | llvm/test/CodeGen/X86/shift-and.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/shift-and.ll b/llvm/test/CodeGen/X86/shift-and.ll index 75e2d233ed1..bb8eaa3c1cb 100644 --- a/llvm/test/CodeGen/X86/shift-and.ll +++ b/llvm/test/CodeGen/X86/shift-and.ll @@ -96,6 +96,21 @@ define i64 @t5(i64 %t, i64 %val) nounwind { ret i64 %res } +define void @t5ptr(i64 %t, i64* %ptr) nounwind { +; X64-LABEL: t5ptr: +; X64: ## BB#0: +; X64-NEXT: andb $-65, %dil +; X64-NEXT: movl %edi, %ecx +; X64-NEXT: shrq %cl, (%rsi) +; X64-NEXT: retq +; X64-NEXT: ## -- End function + %shamt = and i64 %t, 191 + %tmp = load i64, i64* %ptr + %tmp1 = lshr i64 %tmp, %shamt + store i64 %tmp1, i64* %ptr + ret void +} + ; rdar://11866926 define i64 @t6(i64 %key, i64* nocapture %val) nounwind { |
