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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 20:23:46 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 20:23:46 +0000 |
| commit | 22e41c411ef7ebb8f7f9b5d4e2accc2b09e5dd81 (patch) | |
| tree | 6eb06b2ca0b7a3f430f7f4c63e78ef991c967aa4 | |
| parent | 49f9885a2ac6a5b9bd85d66588fccab0de25923b (diff) | |
| download | bcm5719-llvm-22e41c411ef7ebb8f7f9b5d4e2accc2b09e5dd81.tar.gz bcm5719-llvm-22e41c411ef7ebb8f7f9b5d4e2accc2b09e5dd81.zip | |
Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).
llvm-svn: 178286
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/bswap-load-store.ll | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index e8b94bca680..74e811b35cf 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -6606,6 +6606,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, (N->getOperand(1).getValueType() == MVT::i32 || N->getOperand(1).getValueType() == MVT::i16 || (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && + TM.getSubtarget<PPCSubtarget>().isPPC64() && N->getOperand(1).getValueType() == MVT::i64))) { SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. @@ -6629,6 +6630,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, N->getOperand(0).hasOneUse() && (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && + TM.getSubtarget<PPCSubtarget>().isPPC64() && N->getValueType(0) == MVT::i64))) { SDValue Load = N->getOperand(0); LoadSDNode *LD = cast<LoadSDNode>(Load); diff --git a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll index 2aae4150efb..6b60fdd6e1a 100644 --- a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7 +; RUN: llc < %s -march=ppc32 -mcpu=pwr7 | FileCheck %s -check-prefix=X32 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { |
