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authorBill Wendling <isanbard@gmail.com>2010-08-08 01:49:35 +0000
committerBill Wendling <isanbard@gmail.com>2010-08-08 01:49:35 +0000
commit18e853f458caee9676c2e29a39aacb7914d85dc4 (patch)
treed1087f666ed3a0a795688f64ad8524d6fb4bdc1c
parent6ff7161d51a9e5a43fd7e69ab2df69a67fcd12e3 (diff)
downloadbcm5719-llvm-18e853f458caee9676c2e29a39aacb7914d85dc4.tar.gz
bcm5719-llvm-18e853f458caee9676c2e29a39aacb7914d85dc4.zip
Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all. llvm-svn: 110531
-rw-r--r--llvm/include/llvm/Target/Target.td1
-rw-r--r--llvm/include/llvm/Target/TargetInstrDesc.h8
-rw-r--r--llvm/utils/TableGen/CodeGenInstruction.cpp1
-rw-r--r--llvm/utils/TableGen/CodeGenInstruction.h1
-rw-r--r--llvm/utils/TableGen/InstrInfoEmitter.cpp1
5 files changed, 11 insertions, 1 deletions
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index ad1a816a95c..809e088e2b0 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -198,6 +198,7 @@ class Instruction {
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
+ bit isCompare = 0; // Is this instruction a comparison instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
diff --git a/llvm/include/llvm/Target/TargetInstrDesc.h b/llvm/include/llvm/Target/TargetInstrDesc.h
index 8f0a6cb1a68..6a08e8f24c0 100644
--- a/llvm/include/llvm/Target/TargetInstrDesc.h
+++ b/llvm/include/llvm/Target/TargetInstrDesc.h
@@ -105,6 +105,7 @@ namespace TID {
IndirectBranch,
Predicable,
NotDuplicable,
+ Compare,
DelaySlot,
FoldableAsLoad,
MayLoad,
@@ -315,7 +316,7 @@ public:
bool isIndirectBranch() const {
return Flags & (1 << TID::IndirectBranch);
}
-
+
/// isConditionalBranch - Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
@@ -340,6 +341,11 @@ public:
return Flags & (1 << TID::Predicable);
}
+ /// isCompare - Return true if this instruction is a comparison.
+ bool isCompare() const {
+ return Flags & (1 << TID::Compare);
+ }
+
/// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
index 35b54a54271..01a1fe11f53 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -102,6 +102,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isReturn = R->getValueAsBit("isReturn");
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
+ isCompare = R->getValueAsBit("isCompare");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
index 946c2d01a52..b02d0d38f97 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/CodeGenInstruction.h
@@ -123,6 +123,7 @@ namespace llvm {
bool isReturn;
bool isBranch;
bool isIndirectBranch;
+ bool isCompare;
bool isBarrier;
bool isCall;
bool canFoldAsLoad;
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index f28af1589d6..4d3aa5e621c 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -270,6 +270,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isReturn) OS << "|(1<<TID::Return)";
if (Inst.isBranch) OS << "|(1<<TID::Branch)";
if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+ if (Inst.isCompare) OS << "|(1<<TID::Compare)";
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|(1<<TID::Call)";
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