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authorTim Northover <tnorthover@apple.com>2014-05-22 07:41:37 +0000
committerTim Northover <tnorthover@apple.com>2014-05-22 07:41:37 +0000
commit0f6272271e77b3b2b6325141c9798aed6ac966b8 (patch)
treea657fb3cb01cfd41872ae87194542d9836cb4b40
parent71d04225cf752e0324e8ceb116d3618daec08e42 (diff)
downloadbcm5719-llvm-0f6272271e77b3b2b6325141c9798aed6ac966b8.tar.gz
bcm5719-llvm-0f6272271e77b3b2b6325141c9798aed6ac966b8.zip
ARM64: assert if we see i64 -> i64 extend in the DAG.
Should be no change in behaviour, but it makes the intended functionality a bit clearer and means we only have to reason about real extend operations. llvm-svn: 209409
-rw-r--r--llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
index 45a837e69f6..ce4203f321c 100644
--- a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
@@ -369,8 +369,7 @@ getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
return ARM64_AM::SXTH;
else if (SrcVT == MVT::i32)
return ARM64_AM::SXTW;
- else if (SrcVT == MVT::i64)
- return ARM64_AM::SXTX;
+ assert(SrcVT != MVT::i64 && "extend from 64-bits?");
return ARM64_AM::InvalidShiftExtend;
} else if (N.getOpcode() == ISD::ZERO_EXTEND ||
@@ -382,8 +381,7 @@ getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
return ARM64_AM::UXTH;
else if (SrcVT == MVT::i32)
return ARM64_AM::UXTW;
- else if (SrcVT == MVT::i64)
- return ARM64_AM::UXTX;
+ assert(SrcVT != MVT::i64 && "extend from 64-bits?");
return ARM64_AM::InvalidShiftExtend;
} else if (N.getOpcode() == ISD::AND) {
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