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| author | Tim Northover <tnorthover@apple.com> | 2014-05-22 07:40:55 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-22 07:40:55 +0000 |
| commit | 71d04225cf752e0324e8ceb116d3618daec08e42 (patch) | |
| tree | 4bc0e53a4382176448fd2940e202a6bc1773a3e9 | |
| parent | c65a66ddfe5b3a51055bb5d3050d022976ba3cf2 (diff) | |
| download | bcm5719-llvm-71d04225cf752e0324e8ceb116d3618daec08e42.tar.gz bcm5719-llvm-71d04225cf752e0324e8ceb116d3618daec08e42.zip | |
AArch64/ARM64: enable more AArch64 tests.
llvm-svn: 209408
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/sibling-call.ll | 13 |
3 files changed, 9 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll b/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll index 8acf6b792eb..181c69c89b2 100644 --- a/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll +++ b/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s +; arm64 has equivalent tests to these in various files. ;Check for a post-increment updating load. define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind { diff --git a/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll b/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll index e53d6cb339b..75f57c5d2ea 100644 --- a/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll +++ b/llvm/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s +; arm64 has equivalents of these tests separately. define { [2 x <16 x i8>] } @test_vld2q_dup_fx_update(i8* %a, i8** %ptr) { ; CHECK-LABEL: test_vld2q_dup_fx_update diff --git a/llvm/test/CodeGen/AArch64/sibling-call.ll b/llvm/test/CodeGen/AArch64/sibling-call.ll index 20f1062a44d..a08f8cbd702 100644 --- a/llvm/test/CodeGen/AArch64/sibling-call.ll +++ b/llvm/test/CodeGen/AArch64/sibling-call.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -arm64-load-store-opt=0 | FileCheck %s declare void @callee_stack0() declare void @callee_stack8([8 x i32], i64) @@ -73,10 +74,10 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { tail call void @callee_stack16([8 x i32] undef, i64 %b, i64 %a) ret void -; CHECK: ldr x0, -; CHECK: ldr x1, -; CHECK: str x1, -; CHECK: str x0, +; CHECK: ldr [[VAL0:x[0-9]+]], +; CHECK: ldr [[VAL1:x[0-9]+]], +; CHECK: str [[VAL1]], +; CHECK: str [[VAL0]], ; CHECK-NOT: add sp, sp, ; CHECK: b callee_stack16 @@ -91,7 +92,7 @@ define void @indirect_tail() { %fptr = load void(i32)** @func tail call void %fptr(i32 42) ret void -; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, #:lo12:func] -; CHECK: movz w0, #42 +; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func] +; CHECK: movz w0, #{{42|0x2a}} ; CHECK: br [[FPTR]] } |
