[ARM GlobalISel] Legalize G_FNEG for s32 and s64

For hard float, it is legal.

For soft float, we need to lower to 0 - x first, and then we can use the
libcall for G_FSUB. This is undoing some of the canonicalization
performed by the IRTranslator (which introduces G_FNEG when it sees a
0 - x). Ideally, that canonicalization would be performed by a
pre-legalizer pass that would allow targets to opt out of this behaviour
rather than dance around it in the legalizer.

llvm-svn: 322168

2 files changed, 83 insertions, 1 deletions

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index b3bfd2a53ad..fa5a8575710 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -161,7 +161,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
     setAction({G_ICMP, 1, Ty}, Legal);
 
   if (!ST.useSoftFloat() && ST.hasVFP2()) {
-    for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT})
+    for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
       for (auto Ty : {s32, s64})
         setAction({BinOp, Ty}, Legal);
 
@@ -184,6 +184,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
         setAction({BinOp, Ty}, Libcall);
 
     for (auto Ty : {s32, s64}) {
+      setAction({G_FNEG, Ty}, Lower);
       setAction({G_FCONSTANT, Ty}, Custom);
     }
 
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 2beb2485997..4b93610ab99 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -23,6 +23,9 @@
   define void @test_fconstant_float() { ret void }
   define void @test_fconstant_double() { ret void }
 
+  define void @test_fneg_float() { ret void }
+  define void @test_fneg_double() { ret void }
+
   define void @test_fcmp_true_s32() { ret void }
   define void @test_fcmp_false_s32() { ret void }
 
@@ -653,6 +656,84 @@ body:             |
     BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
+name:            test_fneg_float
+# CHECK-LABEL: name: test_fneg_float
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    %0(s32) = COPY %r0
+    ; HARD: [[R:%[0-9]+]]:_(s32) = G_FNEG [[X]]
+    ; SOFT-NOT: G_FNEG
+    ; SOFT-DAG: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; SOFT: ADJCALLSTACKDOWN
+    ; SOFT-DAG: %r0 = COPY [[ZERO]]
+    ; SOFT-DAG: %r1 = COPY [[X]]
+    ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+    ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+    ; SOFT: ADJCALLSTACKUP
+    ; SOFT-NOT: G_FNEG
+    %1(s32) = G_FNEG %0
+    ; CHECK: %r0 = COPY [[R]]
+    %r0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
+name:            test_fneg_double
+# CHECK-LABEL: name: test_fneg_double
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+    %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+    ; HARD: [[R:%[0-9]+]]:_(s64) = G_FNEG [[X]]
+    ; SOFT-NOT: G_FNEG
+    ; SOFT-DAG: [[NEGATIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; SOFT-DAG: [[POSITIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT: ADJCALLSTACKDOWN
+    ; SOFT-DAG: %r{{[0-1]}} = COPY [[NEGATIVE_ZERO]]
+    ; SOFT-DAG: %r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
+    ; SOFT-DAG: %r{{[2-3]}} = COPY [[X0]]
+    ; SOFT-DAG: %r{{[2-3]}} = COPY [[X1]]
+    ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+    ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+    ; SOFT: ADJCALLSTACKUP
+    ; SOFT-NOT: G_FNEG
+    %3(s64) = G_FNEG %2
+    ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+    %4(s32),%5(s32) = G_UNMERGE_VALUES %3(s64)
+    %r0 = COPY %4(s32)
+    %r1 = COPY %5(s32)
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
+...
+---
 name:            test_fcmp_true_s32
 # CHECK-LABEL: name: test_fcmp_true_s32
 legalized:       false