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| author | Vicente Olivert Riera <Vincent.Riera@imgtec.com> | 2016-09-30 10:36:49 +0100 |
|---|---|---|
| committer | Peter Korsgaard <peter@korsgaard.com> | 2016-10-15 13:22:17 +0200 |
| commit | 45c92c60b163abefb0e78fe4f992d7cbbdaa72e8 (patch) | |
| tree | 4d3d1b1a8c94f23d0a3626e3ed14f8526ed130e0 /package/glibc | |
| parent | f62cbd75b7f56d1842c9d59e6779b0e869d164f9 (diff) | |
| download | buildroot-45c92c60b163abefb0e78fe4f992d7cbbdaa72e8.tar.gz buildroot-45c92c60b163abefb0e78fe4f992d7cbbdaa72e8.zip | |
MIPS: replace every BR2_mips_* with the new MIPS CPU options
Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Diffstat (limited to 'package/glibc')
| -rw-r--r-- | package/glibc/glibc.mk | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/package/glibc/glibc.mk b/package/glibc/glibc.mk index 2c32e65fdc..50154e851a 100644 --- a/package/glibc/glibc.mk +++ b/package/glibc/glibc.mk @@ -136,7 +136,7 @@ endef # highly unlikely. The failure mode, if it ever occurs, would be either # that a signalling NaN fails to raise an invalid operation exception or # (more likely) an ordinary NaN raises an invalid operation exception. -ifeq ($(BR2_mips_32r6)$(BR2_mips_64r6),y) +ifeq ($(BR2_MIPS_CPU_MIPS32R6)$(BR2_MIPS_CPU_MIPS64R6),y) define GLIBC_FIX_MIPS_R6 $(SED) 's#10.0.0#4.0.0#' \ $(@D)/sysdeps/unix/sysv/linux/mips/configure \ |
