From 45c92c60b163abefb0e78fe4f992d7cbbdaa72e8 Mon Sep 17 00:00:00 2001 From: Vicente Olivert Riera Date: Fri, 30 Sep 2016 10:36:49 +0100 Subject: MIPS: replace every BR2_mips_* with the new MIPS CPU options Signed-off-by: Vicente Olivert Riera Signed-off-by: Peter Korsgaard --- package/glibc/glibc.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'package/glibc') diff --git a/package/glibc/glibc.mk b/package/glibc/glibc.mk index 2c32e65fdc..50154e851a 100644 --- a/package/glibc/glibc.mk +++ b/package/glibc/glibc.mk @@ -136,7 +136,7 @@ endef # highly unlikely. The failure mode, if it ever occurs, would be either # that a signalling NaN fails to raise an invalid operation exception or # (more likely) an ordinary NaN raises an invalid operation exception. -ifeq ($(BR2_mips_32r6)$(BR2_mips_64r6),y) +ifeq ($(BR2_MIPS_CPU_MIPS32R6)$(BR2_MIPS_CPU_MIPS64R6),y) define GLIBC_FIX_MIPS_R6 $(SED) 's#10.0.0#4.0.0#' \ $(@D)/sysdeps/unix/sysv/linux/mips/configure \ -- cgit v1.2.3