translated_examples/whileloop.v


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// no timescale needed

module whileloop(
input wire [31:0] A,
output reg [3:0] Z
);


  always @(A) begin : P1
    reg [31:0] I;

    Z <= 4'b0000;
    I = 0;
    while ((I <= 3)) begin
      if((A == I)) begin
        Z[I] <= 1'b1;
      end
      I = I + 1;
    end
  end


endmodule