translated_examples/wbit1.v


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// Nearly useless stub, it's here to support generate.vhd
// no timescale needed

module wbit1(
input wire clk,
input wire wrb,
input wire reset,
input wire enb,
input wire din,
output reg dout
);


wire foo;

  always @(clk) begin
    dout <= 1'b1;
  end


endmodule