blob: 53e223d32ff1b43608cf71a6c55e0190f708250d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
// no timescale needed
module ifchain(
input wire clk,
input wire rstn,
input wire enable,
output reg result
);
reg [3:0] counter;
parameter CLK_DIV_VAL = 11;
always @(posedge clk, posedge rstn) begin
if((rstn == 1'b0)) begin
counter <= {4{1'b0}};
result <= 1'b0;
end else begin
// Divide by 2 by default
if((enable == 1'b1)) begin
if((counter == 0)) begin
counter <= CLK_DIV_VAL;
result <= 1'b1;
end
else begin
counter <= counter - 1;
result <= 1'b0;
end
// counter
end
// enable
end
end
endmodule
|