blob: 44793e3d13a731430d17b9cde274ff7820963d18 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity whileloop is port(
A : in integer;
Z : out std_logic_vector(3 downto 0)
);
end whileloop;
architecture rtl of whileloop is
begin
process (A)
variable I : integer range 0 to 4;
begin
Z <= "0000";
I := 0;
while (I <= 3) loop
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
end process;
end rtl;
|