vhdl2vl - vhdl2vl

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added support to entity instantiations	Rodrigo Alejandro Melo	2017-11-28	1	-0/+4
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*	Simple fix to genericmap example	Larry Doolittle	2017-11-18	1	-2/+2
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*	Changes on genericmap due to unsupported port assignment	Rodrigo Alejandro Melo	2017-11-16	1	-2/+2
\| \| \| \|	This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd.
*	Rework some examples so resulting Verilog compiles	Larry Doolittle	2017-11-10	1	-2/+14
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*	Fixes in examples and translated examples to avoid some complains of iVerilog	Rodrigo Alejandro Melo	2017-02-19	1	-2/+1
\| \| \| \| \|	'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog.
*	Changed translated_examples due that Verilog 2001 is now the default	Rodrigo Alejandro Melo	2017-02-17	1	-67/+24
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*	Added command line option --quiet	Rodrigo Alejandro Melo	2017-02-17	1	-21/+0
\| \| \| \| \|	Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples.
*	Space deleted in the <size>'<radix><number> notation	Rodrigo Alejandro Melo	2017-02-09	1	-2/+2
\| \| \| \| \| \| \|	It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified.
*	vhd2vl-2.5	Larry Doolittle	2015-09-20	1	-2/+2
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*	vhd2vl-2.4	Larry Doolittle	2015-09-20	1	-1/+4
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*	vhd2vl-2.3	Larry Doolittle	2015-09-20	1	-2/+2
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*	vhd2vl-2.2	Larry Doolittle	2015-09-20	1	-0/+128