Added command line option --quiet

Used to avoid header on the generated verilog file. Is a problem for regression tests.
Header was removed from translated_examples.

1 files changed, 0 insertions, 21 deletions

diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index 7a5da32..2d66b14 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -1,24 +1,3 @@
-// File genericmap.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
-// vhd2vl settings:
-//  * Verilog Module Declaration Style: 1995
-
-// vhd2vl is Free (libre) Software:
-//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
-//     http://www.ocean-logic.com
-//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
-//   Modifications (C) 2010 Shankar Giri
-//   Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
-//     http://doolittle.icarus.com/~larry/vhd2vl/
-//
-//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
-//   Verilog for correctness, ideally with a formal verification tool.
-//
-//   You are welcome to redistribute vhd2vl under certain conditions.
-//   See the license (GPLv2) file included with the source for details.
-
-// The result of translation follows.  Its copyright status should be
-// considered unchanged from the original VHDL.
-
 // no timescale needed
 
 module test(