1 files changed, 33 insertions, 0 deletions
diff --git a/translated_examples/mem.v b/translated_examples/mem.v
new file mode 100644
index 0000000..18e36c4
--- /dev/null
+++ b/translated_examples/mem.v
@@ -0,0 +1,33 @@
+// no timescale needed
+
+module mem(
+input wire clk,
+input wire rstn,
+input wire en,
+input wire cs,
+input wire [addr_width - 1:0] addr,
+input wire [bus_width - 1:0] din,
+output wire [bus_width - 1:0] dout
+);
+
+parameter [31:0] addr_width=6;
+parameter [31:0] bus_width=14;
+// not implemented
+// not implemented
+
+
+
+
+reg [bus_width - 1:0] mem[255:0];
+reg [addr_width - 1:0] al = 8'h00;
+
+  assign dout = mem[al];
+  always @(posedge clk) begin
+    al <= addr;
+    if(en == 1'b1) begin
+      mem[addr] <= din;
+    end
+  end
+
+
+endmodule