4 files changed, 94 insertions, 7 deletions
diff --git a/examples/dsp.vhd b/examples/dsp.vhd
new file mode 100644
index 0000000..7dedb47
--- /dev/null
+++ b/examples/dsp.vhd
@@ -0,0 +1,32 @@
+-- Nearly useless stub, it's here to support genericmap.vhd
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+
+entity dsp is generic(
+  rst_val   : std_logic := '0';
+  thing_size: integer := 201;
+  bus_width : integer := 24
+);
+    port(
+      -- Inputs
+      clk, rstn : in std_logic;
+      en, start : in std_logic;
+      param : in std_logic_vector(7 downto 0);
+      addr : in std_logic_vector(2 downto 0);
+      din : in std_logic_vector(bus_width-1 downto 0);
+      we : in std_logic;
+      memdin : out std_logic_vector(13 downto 0);
+      -- Outputs
+      dout : out std_logic_vector(bus_width-1 downto 0);
+      memaddr : out std_logic_vector(5 downto 0);
+      memdout : out std_logic_vector(13 downto 0)
+      );
+end;
+
+architecture rtl of dsp is
+    signal foo : std_logic;
+begin
+    process(clk) begin
+       dout <= '1';
+    end process;
+end rtl;
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 33d9363..9da3806 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -38,8 +38,14 @@ architecture rtl of genericmap is
     port(
       -- Inputs
       clk, rstn : in std_logic;
+      en, start : in std_logic;
+      param : in std_logic_vector(7 downto 0);
+      addr : in std_logic_vector(2 downto 0);
+      din : in std_logic_vector(25 downto 0);
+      we : in std_logic;
+      memdin : out std_logic_vector(13 downto 0);
       -- Outputs
-      dout : out std_logic_vector(bus_width downto 0);
+      dout : out std_logic_vector(bus_width-1 downto 0);
       memaddr : out std_logic_vector(5 downto 0);
       memdout : out std_logic_vector(13 downto 0)
       );
@@ -53,12 +59,19 @@ architecture rtl of genericmap is
   signal colour : std_logic_vector(1 downto 0);
 begin
   dsp_inst0 : dsp
+    -- default bus_width is 24
     port map(
     -- Inputs
     clk => clk,
     rstn => rstn,
+    en => '1',
+    start => '0',
+    param => X"42",
+    addr => "101",
+    din => X"111111",
+    we => '0',
     -- Outputs
-    dout => dout,
+    dout => dout(23 downto 0),
     memaddr => memaddr,
     memdout => memdout
   );
@@ -71,8 +84,14 @@ begin
     -- Inputs
     clk => clk,
     rstn => rstn,
+    en => '1',
+    start => '0',
+    param => X"42",
+    addr => "101",
+    din => X"1111",
+    we => '0',
     -- Outputs
-    dout => dout,
+    dout => dout(15 downto 0),
     memaddr => memaddr,
     memdout => memdout
   );
diff --git a/examples/mem.vhd b/examples/mem.vhd
new file mode 100644
index 0000000..90c1d62
--- /dev/null
+++ b/examples/mem.vhd
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mem is
+generic(
+  addr_width : integer := 6;
+  bus_width : integer := 14
+);
+  port (
+    clk : in std_logic;
+    rstn : in std_logic;  -- not implemented
+    en : in std_logic;
+    cs : in std_logic;  -- not implemented
+    addr : in unsigned(addr_width-1 downto 0);
+    din : in unsigned(bus_width-1 downto 0);
+    dout : out unsigned(bus_width-1 downto 0)
+  );
+end entity; 
+
+architecture rtl of mem is
+  type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0);
+  signal mem : mem_Type;
+  signal al : unsigned(addr_width-1 downto 0) := X"00";
+begin
+  dout <= mem(al);  
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      al <= addr;
+      if en = '1' then
+        mem(addr) <= din;
+      end if;
+    end if;
+  end process;
+end architecture;
diff --git a/examples/test.vhd b/examples/test.vhd
index b273e8f..d102a11 100644
--- a/examples/test.vhd
+++ b/examples/test.vhd
@@ -25,7 +25,7 @@ entity test is port(
   base : in std_logic_vector(2 downto 0);
   qtd : in std_logic_vector(21 downto 0);
   -- Outputs
-  dout : out std_logic_vector(25 downto 0);
+  dout : out std_logic_vector(23 downto 0);
   pixel_out : out std_logic_vector(7 downto 0);
   pixel_valid : out std_logic;
   code : out std_logic_vector(9 downto 0);
@@ -46,11 +46,11 @@ component dsp port(
   en, start : in std_logic;
   param : in std_logic_vector(7 downto 0);
   addr : in std_logic_vector(2 downto 0);
-  din : in std_logic_vector(25 downto 0);
+  din : in std_logic_vector(23 downto 0);
   we : in std_logic;
   memdin : out std_logic_vector(13 downto 0);
     -- Outputs
-  dout : out std_logic_vector(25 downto 0);
+  dout : out std_logic_vector(23 downto 0);
   memaddr : out std_logic_vector(5 downto 0);
   memdout : out std_logic_vector(13 downto 0)
 );
@@ -162,7 +162,7 @@ begin
     start => start,
     param => param,
     addr => addr,
-    din => din,
+    din => din(23 downto 0),
     we => we,
     memdin => memdin,
     -- Outputs