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author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-17 00:16:15 -0300 |
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committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-17 00:16:15 -0300 |
commit | 621b5169dea000c5fd393b172290c9d46337299d (patch) | |
tree | b9cf730408d3be039d616d10fa096c44d6866f6c /translated_examples/scientific.v | |
parent | a19f0441854a5602dd8865ea2eed341a5a5056de (diff) | |
download | vhdl2vl-621b5169dea000c5fd393b172290c9d46337299d.tar.gz vhdl2vl-621b5169dea000c5fd393b172290c9d46337299d.zip |
Added command line option --quiet
Used to avoid header on the generated verilog file. Is a problem for regression tests.
Header was removed from translated_examples.
Diffstat (limited to 'translated_examples/scientific.v')
-rw-r--r-- | translated_examples/scientific.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/translated_examples/scientific.v b/translated_examples/scientific.v index e5b301b..c8fc85f 100644 --- a/translated_examples/scientific.v +++ b/translated_examples/scientific.v @@ -1,24 +1,3 @@ -// File scientific.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator -// vhd2vl settings: -// * Verilog Module Declaration Style: 1995 - -// vhd2vl is Free (libre) Software: -// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd -// http://www.ocean-logic.com -// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc -// Modifications (C) 2010 Shankar Giri -// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL -// http://doolittle.icarus.com/~larry/vhd2vl/ -// -// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting -// Verilog for correctness, ideally with a formal verification tool. -// -// You are welcome to redistribute vhd2vl under certain conditions. -// See the license (GPLv2) file included with the source for details. - -// The result of translation follows. Its copyright status should be -// considered unchanged from the original VHDL. - module Scientific( clk |