Simplified iverilog check

3 files changed, 5 insertions, 7 deletions

diff --git a/examples/ifchain2.vhd b/examples/ifchain2.vhd
index 837dace..b002568 100644
--- a/examples/ifchain2.vhd
+++ b/examples/ifchain2.vhd
@@ -2,14 +2,14 @@ LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
 USE IEEE.numeric_std.all;
 
-entity ifchain is port(
+entity ifchain2 is port(
   clk, rstn : in std_logic;
   enable: in std_logic;
   result: out std_logic
 );
-end ifchain;
+end ifchain2;
 
-architecture rtl of ifchain is
+architecture rtl of ifchain2 is
   signal counter : unsigned(3 downto 0);
   constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4);
 begin
diff --git a/translated_examples/Makefile b/translated_examples/Makefile
index 6ab476d..b4bfad1 100644
--- a/translated_examples/Makefile
+++ b/translated_examples/Makefile
@@ -4,10 +4,8 @@ TEMP = ../temp/verilog
 
 all:
 ifneq ($(shell which iverilog),)
-	@mkdir -p $(TEMP)
 	@echo "##### Checking resulting Verilog files with iverilog ###########"
-	@-cd $(TEMP); $(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\
-	iverilog -Wall -y . -t null $(VERILOG);)
+	-cd $(TEMP); iverilog -Wall -y . -t null *.v
 endif
 
 clean:
diff --git a/translated_examples/ifchain2.v b/translated_examples/ifchain2.v
index 53e223d..3208dcf 100644
--- a/translated_examples/ifchain2.v
+++ b/translated_examples/ifchain2.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module ifchain(
+module ifchain2(
 input wire clk,
 input wire rstn,
 input wire enable,