Initial conversion pass VHDL to Verilog

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+Copyright (c) 2017, Raptor Engineering, LLC
+Copyright (c) 2017, International Business Machines Corp.
+All rights reserved.
+Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met: 
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+following disclaimer in the documentation and/or other materials provided with the 
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+contributors may be used to endorse or promote products derived from this software 
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