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* | Merge branch 'stable'Stewart Smith2015-06-051-1/+1
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| * core/mem_region: Create reservations of type REGION_HW_RESERVEDJeremy Kerr2015-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All current users of mem_reserve are actually wanting HW_RESERVED memory; these reservations are for memory initialised pre-skiboot. This change marks these regions as REGION_HW_RESERVED instead of REGION_RESERVED. We also rename mem_reserve to mem_reserve_hw to reflect this change. This fixes an issue where the PRD daemon cannot find reserved ranges (eg, the homer image) that have been created by skiboot itself. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Make cpu_relax() inlineStewart Smith2015-05-291-1/+11
| | | | | | | | | | | | | | | | | | | | This modifies code output when built with GCOV so that the store of counter data is out of some of the loops, thus improving things when built with gcov. Also, likely makes us do even less work when relaxing, so probably a good thing. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge PRD rework from stableStewart Smith2015-05-213-5/+17
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| * prd: Don't expose full opal_prd_msg to kernelJeremy Kerr2015-05-211-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The kernel is only accessing part of struct opal_prd_msg, and doesn't need to know about the rest. This change moves the "internal" parts of opal_prd_msg to a separate header. In order for the kernel to pass full messages between userspace and firmware, it needs the total size of the struct. We put this in the header for the kernel to access. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * hw/prd: Expose prd ranges via device treeJeremy Kerr2015-05-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the prd reserved ranges are present in the reserved-ranges nodes in the device tree. While this works, it's difficult to filter the actual PRD ranges from general reserved memory. This change links the prd ranges into the /reserved-memory nodes, by adding ibm,prd-label properties to those used for PRD. This change adds a prd node to the ibm,opal node too, to giver kernel & userspace information about the prd infrastructure provided by OPAL. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * core: Add mem_region_nextJeremy Kerr2015-05-211-0/+3
| | | | | | | | | | | | | | This change adds a function to iterate mem_regions. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * core: Introduce REGION_HW_RESERVEDJeremy Kerr2015-05-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | This change allows the mem_region code to distinguish reserved memory that was allocated before skiboot init, by introducing a new mem_region_type member. When we extract reserved ranges from the device tree, we mark them with this new type. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * core: Rename mem_region->mem_node to ->nodeJeremy Kerr2015-05-211-1/+1
| | | | | | | | | | | | | | We'll want to store non-memory nodes in this pointer too. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * core: Move free-list locking to a separate per-region lockJeremy Kerr2015-05-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we have a single lock for the entire mem_region system; this protects both the global region list, and the allocations from each region. This means we can't allocate memory while traversing the global region list, as any malloc/realloc/free will try to acquire the mem_region lock again. This change separates the locking into different functions. We keep the mem_region_lock to protect the regions list, and introduce a per-region lock to protect allocations from the regions' free_lists. Then we remove the open-coded invocations of mem_alloc, where we'd avoided malloc() due to the above locking issue. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Add 2MB to skiboot heapStewart Smith2015-05-151-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rearrange memory map slightly, adding in an extra 2MB into skiboot heap. We lost 1MB of HEAP when allowing skiboot binary to be 2MB, and we were starting to get close to not having a lot of room to play with, especially on larger systems. With this patch: - on Tuleta, we now have 4,422,472 free in firmware-heap for runtime. - on Mambo, we have 13,094,080 free Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Make skiboot able to be 2MB rather than 1MBStewart Smith2015-05-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When built with gcov, skiboot is >1MB (closer to 1.5MB) and there were a few assumptions about skiboot being <1MB. The biggest one was that when code got larger, we'd have the sbss section start in the middle of code, so that when we were going to relocate ourselves, we'd only get the first 1MB of skiboot relocated, which excluded the _DYNAMIC section, meaning that relocate() would not find the right sections. We also needed to not start writing over random parts of skiboot. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | core: Move free-list locking to a separate per-region lockJeremy Kerr2015-05-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we have a single lock for the entire mem_region system; this protects both the global region list, and the allocations from each region. This means we can't allocate memory while traversing the global region list, as any malloc/realloc/free will try to acquire the mem_region lock again. This change separates the locking into different functions. We keep the mem_region_lock to protect the regions list, and introduce a per-region lock to protect allocations from the regions' free_lists. Then we remove the open-coded invocations of mem_alloc, where we'd avoided malloc() due to the above locking issue. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | occ: Send self-interrupt to chip with active PSIJoel Stanley2015-05-132-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously asking the OCC of the current chip to generate the self interrupt. If Hostboot does not configure all the PSI Host Bridges, so if the current chip happens to have an unconfigured PSI HB, the chip will never see the interrupt. Instead grab a chip id from the list of configured PSIs, and ask the OCC on that chip to generate the self-interrupt. This adds a pointer to the chip's PSI in struct proc_chip so we can use the current chip's PSI if it is active without having to look through all of them. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Add pr_fmt to do printf/prlog prefixing automagicallyStewart Smith2015-05-121-1/+7
| | | | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Add prlog_once for logging a message only onceJoel Stanley2015-05-071-0/+8
| | | | | | | | | | Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Preload VPD LID and set up fsp_lid_load() for async queued loadingStewart Smith2015-05-073-1/+4
| | | | | | | | | | | | | | | | This means VPD LID is already loaded before we start preloading kernel and initramfs LIDs, thus ensuring VPD doesn't have to wait for them to finish being read from FSP. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Add global CPU job queueStewart Smith2015-05-071-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we have multiple systems trying to start concurrent jobs on different CPUs, they typically pick the first available (operating) CPU to schedule the job on. This works fine when there's only one set of jobs or when we want to bind jobs to specific CPUs. When we have jobs such as asynchronously loading LIDs and scanning PHBs, we don't care which CPUs they run on, we care more that they are not scheduled on CPUs that have existing tasks. This patch adds a global queue of jobs which secondary CPUs will look at for work (if idle). This leads to simplified callers, which just need to queue jobs to NULL (no specific CPU) and then call a magic function that will run the CPU job queue if we don't have secondary CPUs. Additionally, we add a const char *name to cpu_job just to aid with debugging. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Asynchronously preload CAPP microcodeStewart Smith2015-05-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Instead of synchronously waiting for CAPP microcode during PCI probe, start preload of CAPP microcode early in boot so that it's present when we need it during PCI probing. On some platforms (astbmc), flash access is serialized, and prior to this patch, the async preload of BOOTKERNEL would have to finish before loading CAPP ucode would start, needlessly slowing boot. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | astbmc: asynchronous preloading of resourcesStewart Smith2015-05-071-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement start_preload_resource and resource_loaded platform functions for astbmc machines (palmetto, habanero, firestone). This means we start loading kernel and initramfs from flash much earlier in boot, doing things like PCI init concurrently so that by the time we go to boot the payload, it's already loaded. Implementation is a simple queue with a job running on another CPU doing the libflash calls. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | eeh: Fix eeh event handlingAlistair Popple2015-05-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The opal eeh interrupt handlers raise an opal event (OPAL_EVENT_PCI_ERROR) whenever there is some processing required from the OS. The OS then needs to call opal_pci_next_error(...) in a loop passing each phb in turn to clear the event. However opal_pci_next_error(...) clears the event unconditionally meaning it would be possible for eeh events to be cleared without processing them leading to missed events. This patch fixes the problem by keeping track of eeh events on a per-phb basis and only clearing the opal event once all phb eeh events have been cleared. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/ELOG: Remove TCE mapping for host bufferVasant Hegde2015-05-071-1/+1
| | | | | | | | | | | | | | | | elog_write_to_host_buffer is used to pass error log to host. Hence we don't need TCE mapping for this buffer. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Handle SA indicator update notificationVasant Hegde2015-05-071-0/+3
| | | | | | | | | | | | | | | | FSP sends SA indicator update notification via sys param update. Use that info to update cached indicator state. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/SYSPARAM: Introduce update notify system parameter notifierVasant Hegde2015-05-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | FSP sends update system parameter notification asynchronously. Presently no one is using this notification. We just ACK this notification. This patch adds notifier chain so that if someone (like LED) is interested in this notification, they can register and get notification. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Add system attention indicator supportVasant Hegde2015-05-072-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAI is controlled by FSP. This patch adds support to get/set this indicator. Also update OPAL interface so that playload can read/set this indicator. During init, we read this indicator state using MBOX command. OPAL uses MBOX interface to update this SAI. FSP sends update notification whenever there is change in SAI state (except for OPAL initiates updates). We use the notification to update cached SAI state. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Get SAI location code from device treeVasant Hegde2015-05-071-0/+6
| | | | | | | | | | | | | | | | SAI information is available in device tree. This patch parses device tree to get SAI location code information. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Define macro instead of hardcoding led typeVasant Hegde2015-05-071-0/+20
| | | | | | | | | | | | | | | | Define macors for LED related device tree property and its values. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Move led header file to include directoryVasant Hegde2015-05-071-0/+153
| | | | | | | | | | | | | | | | | | | | We want to refer leds header file in hdata. Hence move header file to include directory. No functionality changes. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge branch 'stable', skiboot-5.0.1Stewart Smith2015-05-012-0/+11
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| * Add xscom_ok() and lpc_ok() to check XSCOM and LPC usabilityBenjamin Herrenschmidt2015-05-012-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | his primarily checks whether the caller already holds the corresponding locks to avoid re-entrancy in some of the deep error path such as when XSCOM itself triggers an error log. It will be extended in the case of LPC to also handle known HW error states. We use them to avoid queuing/polling in the BT driver and to discard characters in the UART driver. Note: This will not normally involve a loss of log to the UART as the UART driver is also protected by the console suspend mechanism. So this is a safety mechanism only. This fixes issues where the generation of error logs inside the LPC or XSCOM drivers could cause a re-entrancy (via the BT interface) causing deadlocks. Now, the error logs IPMI messages will be queued up and delivered later on the next poll handler. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Adjust skiboot_cpu_stacks region size according to real max PIRStewart Smith2015-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In skiboot, CPU stacks are indexed by PIR. During boot, we have two ideas about what the actual maximum PIR is: 1) detect CPU type (P7 or P8): we know max PIR is max for that proc (e.g. 1024, 8192) 2) start all CPUs (go through device tree for CPUs that exist). We now know the *actual* CPUs we have and the max PIR. e.g 1, 64, 3319 or whatever Each CPU stack is 16KB. So max CPU stacks size for P7 is 16MB, for P8 is 128MB. The *actual* max for the machine we're booting on is based on max PIR we detect during boot. I have found the following: Mambo: 16kb max (one CPU) P7: 64, meaning 64*16k = 1MB P8: 3320, meaning 3320*16k = 51MB So, currently, we were not reseting the size of the skiboot_cpu_stacks memory region correctly before boot (we construct that part of the device tree as the very last thing before booting the payload), even though the comment in mem_region.c would suggest we were, we weren't. Because code comments are evil and are nothing but filty, filthy lies. With this patch, we now properly adjust the CPU stacks memory region size after we've detected CPU type and after we've found the real max PIR. This saves between about 77MB and 128MB-16kB of memory from being in a reserved region and it'll now be available to the OS to use for things such as cat pictures rather than being firmware stack space waiting for a CPU that will never appear. You can see the difference in skiboot log, "Reserved regions:": Before: ALL: 0x000031a00000..0000399fffff : ibm,firmware-stacks AFTER: Mambo: 0x000031a00000..000031a1ffff : ibm,firmware-stacks P7: 0x000031a00000..000031afffff : ibm,firmware-stacks. P8: 0x000031a00000..000034ddffff : ibm,firmware-stacks Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | pci: Fix presence detect on PHB3Benjamin Herrenschmidt2015-04-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The presence detect bit in the standard root complex config space is not properly implemented on some IBM PHBs. Using it during probe is incorrect. We already have a workaround using the hotplug override "AB" detect bits in the PHB3 code but it somewhat relies on the standard presence detect bit returning false positives, which happened on Venice/Murano but no longer happens in Naples. Similarly, all the slot control stuff in the generic pci_enable_bridge() isn't going to work properly on the PHB root complex and is unnecessary as this code is only called after the upper layers have verified the presence of a valid link on the PHB (the slot power control for the PHB is handled separately). This fixes it all by removing the AB detect flag, and unconditionally using those bits in PHB3 presence detect along with making sure the code in pci_enable_bridge() that manipulates the slot controls is only executed on downstream ports. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | phb3: Add Naples PHB supportBenjamin Herrenschmidt2015-04-152-0/+3
| | | | | | | | | | | | | | | | This detects the new PHB revision and does the appropriate updates to the init sequence. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Add Naples chip supportBenjamin Herrenschmidt2015-04-092-0/+2
|/ | | | | | | | | | This adds the PVR and CFAM ID for the Naples chip. Otherwise treated as a Venice. This doesn't add the definitions for the new PHB revision yet Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Move contents of opal.h to opal-api.hMichael Ellerman2015-04-012-931/+948
| | | | | | | | | | | | | | | | | | | | | Move the contents of opal.h, which is the definition of the OPAL API shared with Linux, into opal-api.h. Recreate opal.h, containing just the include of types.h as well as including opal-api.h and opal-internal.h. We can also remove the #ifdef SKIBOOT, because opal.h is no longer shared with Linux. This gets us to an opal-api.h that is purely a superset of Linux's opal-api.h, ie. the only differences are things that are new in skiboot and haven't yet been added to Linux. Finally update head.S to only include opal-api.h, which is all it needs, and avoids the need for ASSEMBLY guards in opal.h. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Move opal-api.h to opal-internal.hMichael Ellerman2015-04-013-84/+86
| | | | | | | | | | | | | | | | Move the content of opal-api.h, which is currently "Internal header for OPAL API related things" to opal-internal.h. Recreate opal-api.h as an empty header, until the next commit, so as not to break all the includers of it. Include opal-internal.h from opal.h, but not for assembly users as it's all C declarations. Finally we need to adjust include guard names. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Remove opal-internal.hMichael Ellerman2015-04-011-234/+0
| | | | | | | | This seems to have been forgotten when the initial open source release was made. It's never been used in the open source tree at all. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: Add support for cec_power_down() on mamboMichael Ellerman2015-04-011-0/+2
| | | | | | | | | | | Currently when running on mambo OPAL_CEC_POWER_DOWN doesn't work, the simulator keeps running. We can use the magic mambo support instruction with the right opcode to ask mambo to stop the simulation. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* exceptions: Catch exceptions at boot timeBenjamin Herrenschmidt2015-03-311-0/+2
| | | | | | | And print some informations about GPR state, backtrace, etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* add NX register definesDan Streetman2015-03-311-0/+120
| | | | | | | | | | | | | | | | | This only adds defines for various NX registers and their bit values. This doesn't add any code that uses them, and it's possible skiboot won't need to use any of these registers, as they're the error and status registers, which will be monitored/handled from the FSP. So this patch isn't required to add; I added all these while I still thought the kernel driver needed to handle them, and I hate to just throw their definitions away ;-) If skiboot ever does need to use any of the status or err registers, the definitions will already be in place with this patch. This patch shouldn't actually affect the compiled binary at all, since it's only adding unused defines. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* set NX crb input queues to 842 onlyDan Streetman2015-03-311-0/+6
| | | | | | | | | | | | | | | | Set the NX crb input queues to be used by 842 only, by not reserving any input queue slots for the sym or asym engines. This allows the maximum number of 842 crb requests to be queued up, to (hopefully) improve 842 performance. This patch isn't critical, as the default is no extra input queue locations for asym, and only 1 extra input queue location for sym, so this only takes sym's extra location for use by 842. There is 1 each dedicated input queue location for asym and sym (and 842), so this patch won't prevent them from working if support is ever added for them. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* FSP: Serialize FSP MBOX command declarationVasant Hegde2015-03-261-20/+20
| | | | | | | Improve code readability. No functionality changes. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* memboot: Add a memboot flash backendAlistair Popple2015-03-261-0/+2
| | | | | | | | | memboot uses bmc system memory instead of a real flash chip. This patch adds a flash backend for bmc system memory to allow use of the memboot tool (in external/memboot) to boot the system. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal: Handle TB residue and HDEC parity HMI errors on split core.Mahesh Salgaonkar2015-03-263-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of split core, some of the Timer facility errors needs cleanup to be done before we proceed with the error recovery. Certain TB/HDEC errors leaves dirty data in timebase and HDEC registers, which need to cleared before we initiate clear_tb_errors through TFMR[24]. The cleanup has to be done by any one thread from core or subcore. In split core mode, it is required to clear the dirty data from TB/HDEC register by all subcores (active partitions) before we clear tb errors through TFMR[24]. The HMI recovery would fail even if one subcore do not cleanup the respective TB/HDEC register. Dirty data can be cleaned by writing zero's to TB/HDEC register. For un-split core, any one thread can do the cleanup. For split core, any one thread from each subcore can do the cleanup. Errors that required pre-recovery cleanup: - SPR_TFMR_TB_RESIDUE_ERR - SPR_TFMR_HDEC_PARITY_ERROR This patch implements pre-recovery steps to clean dirty data from TB/HDEC register for above mentioned timer facility errors. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal: Recover from TFMR SPURR/PURR parity error.Mahesh Salgaonkar2015-03-261-0/+2
| | | | | | | | | | | | | | | Recovery process for SPURR/PURR parity error: - Set SPURR/PURR Register with valid value or zero - Reset TFMR SPURR/PURR parity error bit. To inject TFMR PURR parity error issue: $ putscom pu.ex 10013281 0004080000000000 -all To inject TFMR SPURR parity error issue: $ putscom pu.ex 10013281 0005080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal: Recover from TFMR DEC parity error.Mahesh Salgaonkar2015-03-261-0/+1
| | | | | | | | | | | | Recovery process for TFMR DEC parity error: - Set DEC Register with all ones. - Reset TFMR DEC parity error bit. To inject TFMR DEC parity error issue: $ putscom pu.ex 10013281 0006080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal: Recover from TFMR HDEC parity error.Mahesh Salgaonkar2015-03-261-0/+1
| | | | | | | | | | | | Recovery process for HDEC parity error: - Reset HDEC Register. - Reset TFMR HDEC parity error bit. To inject HDEC parity error issue: $ putscom pu.ex 10013281 0002080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: add device tree nodes for the core temperaturesCédric Le Goater2015-03-241-0/+1
| | | | | | | | | | This patch simply adds sensors nodes for the core temperatures. It uses the core PIR as a resource identifier to fit in the sensor model. The device tree nodes use the new layout. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: add support to read the core temperaturesCédric Le Goater2015-03-242-0/+27
| | | | | | | | | | | | This patch adds a new sensor family for Digital Temperature Sensors and a new resource class to capture the core temperatures. Each core has four DTS located in different zones (LSU, ISU, FXU, L3). The max of the four temperatures is computed and returned for the core as well as a global trip point value. This is based on the meltbox tool. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: add a platform op to read sensorsCédric Le Goater2015-03-243-0/+63
| | | | | | | | | | This patch introduces an initial framework to define a sensor_read operation per platform. It also proposes a few helper routines to work on the sensor 'handler' which identifies a sensor and attribute in the OPAL_SENSOR_READ call. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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