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| * Merge branch 'skiboot-5.1.x' into skiboot-5.2.xStewart Smith2016-04-271-0/+2
| |\ | | | | | | | | | Merge PHB3 race fix
| | * OPAL:Handle mbox response with bad status:0x24 during FSP terminationMamatha2016-04-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problem Description: During FSP termination/reset, FSP received mbox command from OPAL for "Fetching platform management function data". As FSP is in termination state DMAE operation failed to write memory data to hypervisor, so FSP sent mbox command with response status as 0x24 to OPAL and OPAL committed a predictive log with SRC BB822411 and sent back response status as 0xFE, which FSP IPMI will not understand the failure at the Host and IPMI will log the error. Fix:This patch is to fix when OPAL receives a bad response from FSP 0x24 due to DMAE error, commit informational log and return response status as SUCCESS and for all other bad status response commit predictive log. Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com> Reviewed-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | | hdata: Initialize SPIRA-H structureVasant Hegde2016-04-011-1/+4
|/ / | | | | | | | | | | | | | | | | | | | | | | Previous patch reduced reserved space in spira structure. Now its safe to reduce the memory for spira section from 2K to 1K. Create separate memory section with 1K size for SPIRA-H. Also initialize SPIRA-H. FSP makes use of this information to pass various boot time data (like SPIRA-S, etc) to host. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | hmi: Add handling for NPU checkstopsRussell Currey2016-03-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the NPU detects an unrecoverable error, it will send a HMI. This is problematic since unhandled HMIs will checkstop the entire system, which is not the intended behaviour of a NPU failure. Instead, the NPU emulated PCI devices should be fenced as part of EEH. Add support for handling NPU HMIs. This works by finding the NPU responsible for the HMI, checking its error registers, and sending a recoverable HMI event. The NPU itself cannot actually recover, but the system should not be brought down. Fence mode is set on the NPU, such that any further operations on the NPU will trigger EEH, and it will be subsequently fenced from the system. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | npu: Fix include in headerRussell Currey2016-03-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | If npu.h were to be used by anything that hasn't included io.h, it fails to find the out_be64 symbol. Fix that up by making it a requirement of npu.h. Signed-off-by: Russell Currey <ruscur@russell.cc> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | pci: Add for_each_phb macro for PHB traversalRussell Currey2016-03-311-0/+14
| | | | | | | | | | | | | | | | | | | | Similar to for_each_cpu, adding a for_each_phb makes PHB traversal easy. Suggested-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Remove unused variablesMichael Neuling2016-03-111-2/+0
| | | | | | | | | | | | | | These aren't used, so remove them. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | spcn: add definitions for the PRS command and modifiersCédric Le Goater2016-03-081-0/+94
| | | | | | | | | | | | | | | | The structures and values from the SPCN specification document plus the new PRS modifier 0x1C to retrieve the power supplies watts. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | core/fdt: Remove deivce_tree.hGavin Shan2016-03-081-35/+0
| | | | | | | | | | | | | | | | | | None of the functions declared in the header file are public. This removes the header file. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Enable Simics UART consoleRyan Grimm2016-03-072-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The UART is a simulated ns16550 with memory mapped registers. A /simics dt node is detected and a SIMICS_QUIRK is added to chip quirks similar to MAMBO_CALLOUTS. It can contain an ns16550 dt node with a property console-bar. The LPC UART code is reused and this will work without an LPC bus in the model. Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | cpu: Add helper function to return number of cores available in the chipShilpasri G Bhat2016-02-231-0/+1
| | | | | | | | | | | | | | | | | | get_available_nr_cores_in_chip() takes 'chip_id' as an argument and returns the number of available cores in the chip. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge branch 'stable'Stewart Smith2016-01-211-0/+5
|\| | | | | | | Merge device tree sorting
| * DT sorting testOliver O'Halloran2016-01-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Moved the dt_dump() into test/dt_common.c so that it can be shared between hdata/test/hdata_to_dt.c and core/test/run-device.c run-device.c contains two tests, one basic sorting test and a generate-and-sort test. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: remove trailing whitespace] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * Enable -Werror for -WformatStewart Smith2016-01-211-0/+44
| | | | | | | | | | | | | | | | | | commit 56bc1890b229072513788992d1d29b6f173c13de upstream We create our own inttypes.h to get the correct printf formatting for 64bit numbers. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | nvlink: Add freeze and fence error injectionRussell Currey2016-01-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable NPU freeze and fence injection through debugfs. For example, if a NPU is PCI bus 8, a freeze on PE 1 can be injected with: echo 1:0:0:0:0 >> /sys/kernel/debug/powerpc/PCI0008/err_injct or a fence on PE 2 on PCI bus 9 with: echo 2:1:0:0:0 >> /sys/kernel/debug/powerpc/PCI0009/err_injct These will cause the appropriate EEH event to occur upon a DMA to the NVLink. PE number was added to the npu_dev struct to enable this. Signed-off-by: Russell Currey <ruscur@russell.cc> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | nvlink: Add fence mode emulation for NPUsRussell Currey2016-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | As NPUs are emulated PCI devices, they do not get physically fenced as real PCI devices do. As such, when the device is in a state that it should be fenced, we need to emulate this behaviour by returning all 1s in config space reads. This will be utilised by error injection in subsequent patches. Signed-off-by: Russell Currey <ruscur@russell.cc> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge OPAL_CONSOLE_FLUSH from stableStewart Smith2016-01-122-3/+4
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| * Add OPAL_CONSOLE_FLUSH to the OPAL APIRussell Currey2016-01-122-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uart consoles only flush output when polled. The Linux kernel calls these pollers frequently, except when in a panic state. As such, panic messages are not fully printed unless the system is configured to reboot after panic. This patch adds a new call to the OPAL API to flush the buffer. If the system has a uart console (i.e. BMC machines), it will incrementally flush the buffer, returning if there is more to be flushed or not. If the system has a different console, the function will have no effect. This will allow the Linux kernel to ensure that panic message have been fully printed out. The existing synchronous flushing mechanism used in OPAL's shutdown and reboot routines has been refactored into a helper that repeatedly calls the new partial flush function. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | hw/bt: fix IPMI_GET_BT_CAPS definitionCédric Le Goater2016-01-081-1/+1
| | | | | | | | | | | | | | | | | | Specified in IPMI docs: http://www.intel.com.au/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf page 587 under BMC Device and Messaging Command Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge branch 'stable'Stewart Smith2015-12-031-0/+1
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| * FSP: Give up PSI link on shutdownAnanth N Mavinakayanahalli2015-12-011-0/+1
| | | | | | | | | | | | | | | | | | Since we are anyway on the way to standby and apparently the other hypervisor also does this. Tested-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | libflash: enable 4b mode on BMC SPI flashJoel Stanley2015-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We already support larger parts on the host flash, but the BMC has always had a 16MB part, so we did not need to enable the 4b addressing mode. This enables the 4b addressing mode when the flash is larger than 16MB. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Drop support for p5ioc2Daniel Axtens2015-11-184-423/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p5ioc2 is used by approximately 2 machines in the world, and has never ever been a supported configuration. Not only is the code virtually unused and very tricky to test, but keeping it around is making life unnecessarily difficult: - It's more complexity to manage for things such as PCI slot support - It's more code for static analysis to cover, which means more time fixing bugs that affect no-one. - It's bloating every single install of skiboot for no benefit. - It's reducing coverage stats, which is sad. Drop p5ioc2. Signed-off-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | hw/bt: Ask the BMC for its BT interface capabilitiesCyril Bur2015-11-171-0/+1
| | | | | | | | | | Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | PCI: use define for wanting dynamic PHB id for pci_register_phbStewart Smith2015-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | No functional change, but static analysis showed up the oddity of something that is generally unsigned (opal_id) having a signed value assigned to it. Took the opportunity to use a define to increase readability. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Enable -Werror for -WformatStewart Smith2015-11-161-0/+44
| | | | | | | | | | | | | | We create our own inttypes.h to get the correct printf formatting for 64bit numbers. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | occ: hbrt: Change the OCC reset orderShilpasri G Bhat2015-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Modify the OCC reset order such that master OCC is reset after the slave OCCs are reset. In Tuleta/Alpine systems 'proc0' will always be the master OCC, which has to be stopped last when FSP sends OCC_RESET command to Opal. This fixes BZ 119718, SW289036 Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge branch 'stable'Stewart Smith2015-11-121-0/+1
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| * FSP: Handle DPO initiated CEC shutdown with FSP in RRAnanth N Mavinakayanahalli2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | In a scenario where the DPO has been initiated, but the FSP then went into reset before the CEC power down came in, OPAL may not give up the link since it may never see the PSI interrupt. So, if we are in dpo_pending and an FSP reset is detected via the DISR, give up the PSI link voluntarily. Tested-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * console: Completely flush output buffer before power down and rebootRussell Currey2015-11-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Completely flush the output buffer of the console driver before power down and reboot. Implements the flushing function for uart consoles, which includes the astbmc and rhesus platforms. Adds a new function, flush(), to the con_ops struct that allows each console driver to specify how their output buffers are flushed. In the cec_power_down and cec_reboot functions, the flush function of the driver is called if it exists. This fixes an issue where some console output is sometimes lost before power down or reboot in uart consoles. If this issue is also prevalent in other console types then it can be fixed later by adding a .flush to that driver's con_ops. Signed-off-by: Russell Currey <ruscur@russell.cc> [stewart@linux.vnet.ibm.com: reduce diff size, change flush function name] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | sparse: fix endian conversion for MDST tableStewart Smith2015-11-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hdata/spira.c:94:25: warning: incorrect type in initializer (different base types) hdata/spira.c:94:25: expected unsigned long long [unsigned] [usertype] addr hdata/spira.c:94:25: got restricted beint64_t [usertype] <noident> hdata/spira.c:95:25: warning: incorrect type in initializer (different base types) hdata/spira.c:95:25: expected unsigned int [unsigned] [usertype] type hdata/spira.c:95:25: got restricted beint32_t [usertype] <noident> hdata/spira.c:96:25: warning: incorrect type in initializer (different base types) hdata/spira.c:96:25: expected unsigned int [unsigned] [usertype] size hdata/spira.c:96:25: got restricted beint32_t [usertype] <noident> hdata/spira.c:99:25: warning: incorrect type in initializer (different base types) hdata/spira.c:99:25: expected unsigned long long [unsigned] [usertype] addr hdata/spira.c:99:25: got restricted beint64_t [usertype] <noident> hdata/spira.c:100:25: warning: incorrect type in initializer (different base types) hdata/spira.c:100:25: expected unsigned int [unsigned] [usertype] type hdata/spira.c:100:25: got restricted beint32_t [usertype] <noident> hdata/spira.c:101:25: warning: incorrect type in initializer (different base types) hdata/spira.c:101:25: expected unsigned int [unsigned] [usertype] size hdata/spira.c:101:25: got restricted beint32_t [usertype] <noident> This also means we use proper conversions in fsp-mdst-table.c This means no actual change for skiboot as it's BE. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | sparse: opal_register() is CPU native endian argumentsStewart Smith2015-11-091-1/+1
| | | | | | | | | | | | | | | | token is CPU native endian rather than BE as this function is only ever called from within skiboot itself to maintain internal tables of what OPAL calls are registered. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Fixup sparse endian annotations for opal events and masksStewart Smith2015-11-091-2/+2
| | | | | | | | | | | | This fixes many spurious sparse warnings Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | opal_table_entry members should be native endianStewart Smith2015-11-091-2/+2
| | | | | | | | | | | | | | Since the opal_table is just internal, it should be in native endian rather than forcing it to be BE. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Properly annotate types.h for sparseStewart Smith2015-11-091-3/+4
| | | | | | | | | | | | This way we don't get hundreds of false warnings from sparse r.e. endian Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Skip OCCs for chip that has occ_functional set to falseStewart Smith2015-11-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some simulation environments, we simulate a system close to an ibm-fsp system but with a crucial difference: we don't simulate OCCs. This means that for a P8 (well, a simulated one) that looks like it's part of a ibm-fsp system, we'd wait around for about a minute to be asked to start OCCs and for the OCCs to start. Obviously, this would never happen and we'd hit the OCC initialization timeout (correctly) logging an error. However, in this simulation environment, it isn't an error as the required information to work out it isn't an error is (at least now) provided in hdat under 'OCC Functional State'. Previously, the ibm,occ-functional-state property was just passed through the device tree to the host through the XSCOM node and skiboot ignored it. This patch takes note of occ-functional-state and skips waiting for OCCs on any chips that have been marked as having non functional OCC. In such simulation environments this means we: a) don't log an error that isn't really an error b) boot 1 minute quicker as we don't hit the timeout. Tested-by: Gajendra B Bandhu1 <gbandhu1@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | console: Completely flush output buffer before power down and rebootRussell Currey2015-11-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Completely flush the output buffer of the console driver before power down and reboot. Implements the flushing function for uart consoles, which includes the astbmc and rhesus platforms. Adds a new function, flush(), to the con_ops struct that allows each console driver to specify how their output buffers are flushed. In the cec_power_down and cec_reboot functions, the flush function of the driver is called if it exists. This fixes an issue where some console output is sometimes lost before power down or reboot in uart consoles. If this issue is also prevalent in other console types then it can be fixed later by adding a .flush to that driver's con_ops. Signed-off-by: Russell Currey <ruscur@russell.cc> [stewart@linux.vnet.ibm.com: reduce diff size, change flush function name] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | slw: Move add_cpu_idle_state_properties() to add_opal_node()Shilpasri G Bhat2015-10-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | 05f52a8dd7c7e402896e049fd24f83d56b70aff4 core: Setup the OPAL DT node before platform probe add_cpu_idle_state_properties() was made local to slw.c in the above commit which caused p7 systems to not populate the nap idle state in DT. So moving add_cpu_idle_state_properties() to add_opal_node to fix this bug. Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Nvlink: Add NPU PHB functionsAlistair Popple2015-10-263-1/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the NPU Nvlink PHB type. It provides access to each nvlink in the system by exposing them as PCIe devices under a NPU PHB type. Each PCIe device has a configuration space implemented in software which indicates the base address of the DL/TL/PL registers required by the device drivers. It also presents one LSI per device which is used to signal device drivers of changes in device status. The configuration space also adds a vendor specific capability which is used primarily by device drivers to power on an train the IBM PHY. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | include/pci-cfg.h: Add PCI vendor specific capability definitionsAlistair Popple2015-10-261-0/+13
| | | | | | | | | | Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | include/bitutils.h: Add macros for 16-bit constantsAlistair Popple2015-10-261-0/+3
| | | | | | | | | | Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | PCI: Trace device node from PCI deviceGavin Shan2015-10-261-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When nvLink and nVida's GPU included in PCI topology, we have the emulated PCI devices to represent nvLinks, which is associated with the real GPU PCI device with help of device-tree. The patch introduces one more field "dn" to "struct pci_device" to make the job easier. The patch also adds one more PHB operations "device_node_fixup", which is to be called when populating PCI device node so that we have chance to link the emulated PCI device and the real GPU device through device tree. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | PCI: Cache PCI device IDsGavin Shan2015-10-261-0/+3
| | | | | | | | | | | | | | | | | | The patch caches IDs (vendor, device, sub-vendor, sub-device and class) for PCI devices. Those IDs could be used to identify one specific PCI device later. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | Merge fix for soft lockup on TB errors from branch 'stable'Stewart Smith2015-10-141-0/+1
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| * opal/hmi: Fix the soft lockup issue on HMI for certain TB errors.Mahesh Salgaonkar2015-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A while loop from wait_for_subcore_threads() function loops until one thread from each subcore completes the pre-cleanup task and sets a cleanup done bit. while (!(*(this_cpu()->core_hmi_state_ptr) & HMI_STATE_CLEANUP_DONE)) cpu_relax(); Without a memory barrier we see that the compiler optimizes the above while loop not to re-fetch the data from memory pointed by this_cpu()->core_hmi_state_ptr. This makes CPU to spin infinitely even though the other CPUs have modified the data causing soft lockup in kernel. There are two ways to fix this, 1) introduce volatile specifier to force re-read the fresh value from the memory. 2) Add barrier() call to cpu_relax(). Second approach will avoid similar bugs in future. This patch uses the second approach to fix this issue. This patch also introduces a timeout for the while loop to handle a worst situation where all other threads are badly stuck without setting a cleanup done bit. Under such situation timeout will help to avoid soft lockups and report failure to kernel. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: add explanation as to why we don't use timebase for timeout] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | PCI: Introduce config register filterGavin Shan2015-10-081-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have to provide the emulated result for PCI config register access on some devices to eleminate the gap between hardware and software. One example would be the 0x28 (prefetchable memory window upper 32-bits) of the root complex on Naples isn't writable. Linux kernel relies on that to detect 64-bits window successfully. This introduces config register filter to PCI device to eleminate above gap. Each PCI device maintains a list of filters, which are populated when the PCI device is initialized. When PCI config space is accessed, the filter is searched to override the result from user (write) or hardware (read) if necessary. Reported-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | interrupts: Convert P8 IRQ assignment to functionsAlistair Popple2015-10-082-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupts on P8 are currently hard-coded using macros in include/interrupts.h. The new P8NVL processor has an extra PHB meaning it supports 4 PHBs in total which leads to the following assert fail when booting P8NVL based systems: [6614913194,3] register IRQ source overlap ! [6620562844,3] new: 2000..27f7 old: 2000..27f7 [6870377440,0] Assert fail: core/interrupts.c:67:0 This patch converts the existing macros to function calls so that different platforms can support extra PHBs at the expense of a reduced maximum number of chips. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | pci: Use a fixed numbering of PHBs on OPAL and improve log consistencyBenjamin Herrenschmidt2015-10-071-1/+1
|/ | | | | | | | | | | | | | On P8, we calculate the OPAL ID of the PHB as a function of the physical chip number and PHB index on that chip. P7 continues using "allocated" numbers for now. We also consistently print the PHB ID as a 4-digit hex number which facilitates decoding it, and print the chip:index location in the probe code to make it easier to correlate log entries. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: use next_chip rather than get_chip] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PHB3: Retry fundamental resetGavin Shan2015-10-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | When issuing fundamental reset on below IPR adapter that seats behind root complex, there is 50% possibility that the link fails to come up after the reset. In that case, the adapter's config space is blocked and it's not usable. host# lspci -ns 0004:01:00.0 0004:01:00.0 0104: 1014:034a (rev 01) host# lspci -s 0004:01:00.0 0004:01:00.0 RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) (rev 01) This introduces another PHB3 state (PHB3_STATE_FRESET_START) allowing to redo fundamental reset if the link doesn't come up in time at the first attempt, to improve the robustness of PHB's fundamental reset. If the link comes up after the first reset, the 2nd reset won't be issued at all. Reported-by: Paul Nguyen <nguyenp@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* centaur: Add indirect XSCOM supportBenjamin Herrenschmidt2015-10-011-0/+12
| | | | | | | | | It works just like P8, we copy the code for now rather than make it somewhat common due to our locking differences and to limit the risk close to release. We can refactor later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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