summaryrefslogtreecommitdiffstats
path: root/include
Commit message (Collapse)AuthorAgeFilesLines
...
* interrupts: Expose irq_source and change prototypes of all opsBenjamin Herrenschmidt2016-07-131-6/+17
| | | | | | | | | | | | This makes irq_source public, and change all irq_source_ops to take the source pointer as a first argument (they can still dig the void * data out of that). This will allow us to embed/wrap it for XIVE later on. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Move around comment in interrupts.hBenjamin Herrenschmidt2016-07-131-33/+32
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fsp-leds: add () around macrosStewart Smith2016-07-111-2/+2
| | | | | | | | | | found by Smatch static analysis (http://smatch.sourceforge.net/): hw/fsp/fsp-leds.c:576 fsp_msg_set_led_state() warn: the 'FSP_LED_EXCL_FAULT' ma\ cro might need parens hw/fsp/fsp-leds.c:583 fsp_msg_set_led_state() warn: the 'FSP_LED_EXCL_IDENTIFY'\ macro might need parens Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Add basic P9 LPC read/write opsBenjamin Herrenschmidt2016-07-081-0/+1
| | | | | | | | | | We still need to review interrupts handling etc... Also update the example device-tree for SIMICS Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb4: Add initial supportBenjamin Herrenschmidt2016-07-085-2/+701
| | | | | | | | | | This adds the base support for the PHB4. It currently only support the M32 window, EEH or in general error recovery aren't supported yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: update (C) year, fix indenting] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: get_reserved_pe_number() needs to take the PHB as argumentBenjamin Herrenschmidt2016-07-081-1/+1
| | | | | | | | The value might be different for different PHB instances Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* XIVE: Base XIVE support for OPAL XICS emulation callsBenjamin Herrenschmidt2016-07-084-4/+390
| | | | | | | | | | | | | This provides basic initialization of the XIVE along with some OPAL calls to emulate an old-style XICS which will initially be used by Linux for backward compatibility. The current implementation is limited to one priority and doesn't expose much to Linux for future exploitation mode yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* interrupts: Add eoi() callback in preparation for XIVE supportBenjamin Herrenschmidt2016-07-081-0/+41
| | | | | | | | This will be used by the XICS emulation in order to EOI the sources themselves. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Timebase quirk for slow simulators like AWAN and SIMICSBenjamin Herrenschmidt2016-07-062-1/+2
| | | | | | | | | | | This will internally pretend the timebase is running 1000 times slower, which reduces some otherwise really terrible delays in some simulators. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: move cfam_chipid cleanup into own patch] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* devicetree: Add dt_node_is_enabled()Benjamin Herrenschmidt2016-07-061-0/+2
| | | | | | | | | | This accessor tests the "status" property allowing us to represent disabled devices in the device-tree. It will be used by PHB4 initially but its usage could be made more widespread. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* uart: Cleanup initialization and remove simulator hackBenjamin Herrenschmidt2016-07-062-2/+2
| | | | | | | | | | Add more generic support for MMIO based UARTs, simplify code, use common initialization, and clean up the device-tree representation as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* bitutils: Add PPC_BITMASK8Benjamin Herrenschmidt2016-07-061-0/+1
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* chip: Add more P9 accessors for converting to/from PIRBenjamin Herrenschmidt2016-07-061-1/+9
| | | | | | | | | To access a local CPU number within a chip essentially, will be used by XIVE Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* POWER9: Add XSCOM related definitionsBenjamin Herrenschmidt2016-07-062-2/+43
| | | | | | | | Macros for EP/EX/EC accesses and some register definitions Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Reserve OPAL API numbers for XICS emulation for XIVEStewart Smith2016-07-061-1/+5
| | | | | | | | | Additionally, we put in some skeleton docs for what's coming, key points being that this is for P9 and above, relies on a device being present in the device tree and is modelled on the PAPR calls. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/xscom: Reset XSCOM engine after finite number of retries when busyVipin K Parashar2016-07-052-0/+7
| | | | | | | | | | | | | | OPAL retries XSCOM read/write operations forever till it succeeds. This can cause XSCOM ops to hang forever when XSCOM engine remains busy for some reason. Changed it to retry XSCOM operations only XSCOM_BUSY_MAX_RETRIES number of times instead of retrying forever. Also added logic to reset XSCOM engine after XSCOM_BUSY_RESET_THRESHOLD number of retries to unblock it when it remains busy. Cc: stable # 9c2d82394fd2 ("xscom: Return OPAL_WRONG_STATE on XSCOM ops..") Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: supply ibm,dec-bits via devicetreeOliver O'Halloran2016-07-011-0/+1
| | | | | | | | | | | | | ISAv3 adds a mode to increase the size of the decrementer from 32 bits. The enlarged decrementer can be between 32 and 64 bits wide with the exact value being implementation dependent. This patch adds support for detecting the size of the large decrementer and populating each CPU node with the "ibm,dec-bits" property. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: rename enable_ld() to enable_large_dec()] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fsp/op-panel: Fix out of bounds array access and #define display dimensionsSuraj Jitindar Singh2016-06-301-0/+4
| | | | | | | | | | | | | | | | | | In the function __opal_write_oppanel() coverity complains about an out of bounds array access. While the pointer is never actually dereferenced, this isn't immediately obvious from the code. Additionally the number and length of the lines on the operator panel display are hard coded into the function. While we are here we might as well move these into a #define statement. Rework the code in __opal_write_oppanel() where the message is copied into the buffer so that coverity won't complain about an out of bounds array access and so that it is line number and length agnostic (now relying on the #defined values). Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* nvlink: Print error message when NPU is fencedRussell Currey2016-06-211-0/+2
| | | | | | | | | | | | | | | NPU fences aren't recoverable, and as such, would require user intervention to have a working system again. The fence will be picked up by the kernel through EEH, but this doesn't happen until the NPU is used for something. So, let's print a message so it's obvious when this happens. A helper function was added to reduce duplication. This also enables code in skiboot to un-fence a NPU, which is useful to NPU developers but very stupid otherwise. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fwts: Add FWTS annotations for NPU errorsStewart Smith2016-06-201-3/+0
| | | | | | | We also remove the NPUERR macros so that the FWTS parsing magic can construct find the prlog statements. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fix for typosFrederic Bonnard2016-06-201-1/+1
| | | | | | | | | While reviewing the Debian packaging, codespell found those. Most proposed fixes are based on codespell's default dictionnary. Signed-off-by: Frederic Bonnard <frediz@linux.vnet.ibm.com> Reviewed-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Allow adding idle states to power-mgt node in mamboShreyas B. Prabhu2016-06-201-2/+1
| | | | | | | | | | | | | | | | | | | This patch removes the check which prevents adding any idle state to "power-mgt" node in mambo. Power8 exposes 3 idle states- nap, fast-sleep and deep-winkle. While fast-sleep depends on SCOMs and deep-winkle depends on SCOMs/SLW, nap has no such dependencies and it can be enabled in mambo. Current code checks for "fast-sleep" in hostboot provided "ibm,enabled-idle-states" dt node for adding fast-sleep and checks for presence of SLW for adding winkle to "power-mgt". Hence with this change only nap will be added to "power-mgt" node in mambo on Power8. On Power9, this patch enables all idle states which don't need SLW. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Move macros associated with power-mgt nodes to opal-api.hShreyas B. Prabhu2016-06-201-2/+19
| | | | | | | | | Move macros associated with cpuidle fields of power-mgt device tree nodes to opal-api.h This patch does not change any functionality. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Add Power9 idle states to power-mgt dt nodeShreyas B. Prabhu2016-06-201-0/+10
| | | | | | | | | | | | | | | | | | | POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. This SPR subsumes PMICR. This patch adds the supported idle states to power-mgt dt node. It also introduces ibm,cpu-idle-state-psscr and ibm,cpu-idle-state-psscr-mask entries which exposes the value to be written to PSSCR to enter a given stop state. These entries replaces POWER8's counterparts ibm,cpu-idle-state-pmicr and ibm,cpu-idle-state-pmicr-mask. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/opal: Support PCI slot and new APIsGavin Shan2016-06-142-74/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The various reset requests are completed by PHB's callbacks. All of them (except reset on IODA table or error injection) are covered by PCI slot. opal_pci_poll() faces similar situation. This reimplements opal_pci_reset() and opal_pci_poll() based on the callbacks provided by PCI slot instead of PHB. Also, couple of new APIs are introduced based on the callbacks in PCI slot as below: * opal_pci_get_presence_state(): Check if there is adapter presented behind the specified PHB or PCI slot. * opal_pci_get_power_state(): Returns power supply state (on or off) on the specified PHB or PCI slot. * opal_pci_set_power_state(): Sets power supply state (on or off) on the specified PHB or PCI slot. Besides, the state can be (offline or online) without changing the PCI slot's power state. Eventually, the definition of unused PHB's callbacks are removed. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Use PCI slot in enumerationGavin Shan2016-06-141-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | During PCI enumeration, the root complex's link and fundamental reset are carried out by PHB's callbacks which are replaced by the corresponding PCI slot's callbacks. Also, the hotplug related device node properties are populated based on the PCI slot info that is included in PCI slot now. This uses PCI slot in enumeration: * Use PCI slot's callbacks for fundamental reset and link status retrieval in PCI enumeration. * Simplify the code by removing traditional PCI/PCI-x related logic as we don't have PCI/PCI-X root complex. * Replace pci_add_slot_properties() with pci_slot_add_properties() to populate PCI slot properties in device-tree. * PHB is always not hotpluggable. No hotpluggable properties in its device node are needed. * Remove "struct pci_slot_info" definition as its info is included in "struct pci_slot". Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Support PHB slotGavin Shan2016-06-141-24/+28
| | | | | | | | | | | The patch refactors functions used for PHB slot management for PHB3. Also, PHB slots are created before platform's PHB setup hook (platform.pci_setup_phb()). That means the platforms can override the properties or methods of the PHB slot if necessary. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Remove useless commentsGavin Shan2016-06-141-2/+0
| | | | | | | | | | This removes the useless comments as the I2C based power managment is covered by this series of patches and the left items in the FIXUP aren't needed any more. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/p7ioc: Support PHB slotGavin Shan2016-06-141-25/+23
| | | | | | | | | | This refactors functions used for PHB slot management for P7IOC. Also, PHB slots are created before platform's PHB setup hook (platform.pci_setup_phb()). That means the platforms can override the properties or methods of the PHB slot if necessary. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Support PCI slotGavin Shan2016-06-144-55/+277
| | | | | | | | | | | | | | | | | | | Every PCIE bridge port or PHB is expected to be bound with PCI slot , to which various PCI slot's functionalities are attached (e.g. power, link, reset). This supports PCI slot: * PCI slot is reprsented by "struct pci_slot". * "struct pci_slot_ops" represents the functions supported on the PCI slot. It's initialized by PCI slot core at the beginning and allowed to be overrided by platform partially or completely. * On PCI hot plugging event, the PCI devices behind the slot are enumarated. Device sub-tree is populated and sent to OS by OPAL message. * On PCI hot unplugging event, the PCI devices behind the slot are destroyed. Device sub-tree is removed and the slot is powered off. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Return value for struct phb_ops::device_initGavin Shan2016-06-141-1/+2
| | | | | | | | | | This adds @data argument and "int" return value for struct phb_ops:: device_init() so that it can be called in pci_walk_dev() directly to reinitialize the PCI devices behind the specified slot in subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Extend pci_restore_bridge_buses() for PCI slotGavin Shan2016-06-141-1/+1
| | | | | | | | | | | | Currently, pci_restore_bridge_buses() restores the assigned bus ranges for all PCI bridges behind the specified PHB. This extends the function and allows doing same thing for the PCI bridges behind the specified slot. The extended functionality is going to be used by PCI hotplug logic in the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Extend pci_walk_dev() for PCI slotGavin Shan2016-06-141-0/+1
| | | | | | | | | | | Currently, pci_walk_dev() iterates all PCI devices behind the specified PHB. This extends the function to allow iteration on PCI devices behind the specified PCI slot so that it can be used by PCI hotplug logic in the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Fix wrong reserved PE# in enumerationGavin Shan2016-06-141-0/+1
| | | | | | | | | | | | | | | When scanning to non-existing PCI device, EEH (frozen) error is usually happening. We clear the unexpected frozen PE state after it. The reserved PE number is assumed to be 0 wrongly. So the frozen state on the reserved PE number isn't cleared properly. This introduces struct phb_ops::get_reserved_pe_number() to retrieve the reserved PE number from platforms. Then the EEH frozen state checking and clearing are applied to the reserved PE number. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Introduce opal_get_device_tree()Gavin Shan2016-06-141-1/+2
| | | | | | | | | This introduces OPAL API opal_get_device_tree() to get the device sub-tree. It's going to be used in PCI hot add path. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Allow to exclude root nodeGavin Shan2016-06-141-1/+1
| | | | | | | | | | | | The root node is excluded in the device sub-tree created during PCI hot add time. This adds one extra argument @exclusive to flatten_dt_node(), __create_dtb() and create_dtb() to indicate the root node should be excluded or not. The changes are going to be used by PCI hot add path and it's not affecting anything at present. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/p8-i2c: Allow to set I2C request timeoutGavin Shan2016-06-141-0/+9
| | | | | | | | | | | | | | | | | | Prior to PCI enumeration, the PHB slot's power state might be changed during fundamental reset. The fundamental reset is implemented by state machine and it's driven by a polling mechanism in predetermined interval (A). On the other hand, PCI slot's power supply is controlled by I2C chip on Firenze platform. It means the PCI slot's power supply state is changed through I2C request which has a timeout timer running in variable interval (B). Comparing to (A), (B) is small and short. That means I2C timeout is reached before first poll running in interval of (A). It's unexpected behaviour. This allows to set I2C request timeout ((B)) to avoid the issue. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Add support for CAPP DMA modeIan Munsie2016-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The XSL used in the Mellanox CX4 card uses a DMA mode of CAPI, which requires a few registers configured specially. In addition to enabling the mode, - The CAPP only owns some of the PHB read buffers, and must be configured to use the correct ones, and the self-snoop configured for the same ones. - The tve needs to be configured to allow the card to access all kernel memory as it uses DMA accesses to read the scheduled process area from the kernel, among other things. These cannot be configured unconditionally, as doing so will break existing CAPI devices that do not use DMA mode. This adds a new mode to the OPAL_PCI_SET_PHB_CAPI_MODE API to enable CAPI in DMA mode. Since the snoop on/off modes write to the capi snoop configuration register, which is configured differently in DMA mode, it uses the redundant bits from the apc master powerbus control register to determine if it should configure the register for DMA mode rather than requiring any more permutations of the mode parameter. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-api: Fix typo in EPOW event handling descriptionVipin K Parashar2016-06-081-1/+1
| | | | | | | Fix typo in EPOW event handling description in include/opal-api.h. Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdata: Make hdata_to_dt more suitable for fuzzingStewart Smith2016-05-181-1/+1
| | | | | | | | We make parse_hdat() return success/failure rather than assert. This allows the hdata_to_dt binary to gracefully error out rather than assert, which is useful when throwing it at a fuzzer. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add base POWER9 supportMichael Neuling2016-05-103-0/+25
| | | | | | | | | | | Add PVR detection, chip id and other misc bits for POWER9. POWER9 changes the location of the HILE and attn enable bits in the HID0 register, so add these definitions also. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: Fix Numbus typo, hdata_to_dt build fixes] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Abstract HILE and attn enable bit definitions for HID0Michael Neuling2016-05-101-2/+2
| | | | | | | | Abstract HILE and attn enable bits definitions for HID0 in case these locations randomly change in future chip revisions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Disable attn instruction on bootMichael Neuling2016-05-101-0/+1
| | | | | | | | | | | | Currently we don't touch the attn enable bit in HID0 on boot. When attn is enabled, it's available everywhere including HV=0. This is very dangerous for the host kernel. This explicitly disables the attn instruction on all CPUs on boot. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/lpc: Log LPC SYNC errors as OPAL_PLATFORM_ERR_EVT errorsVipin K Parashar2016-05-031-0/+1
| | | | | | | | | Log LPC SYNC errors as OPAL_PLATFORM_ERR_EVT errors with generic predictive error (OPAL_PREDICTIVE_ERR_GENERAL) severity. Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use const char* rather than strcpy] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Remove pci_put_phb()Gavin Shan2016-05-031-1/+0
| | | | | | | | | | | | | | pci_{get,put}_phb() were introduced to increase/decrease refcount or similar thing to PHB. They should show up in pairs and some code is obvious breaking the semantics, but the logic is good as pci_put_phb() does nothing. As we do not maintain refcount for PHB and we should not have PHB unplugging in near future, it simply drops pci_put_phb(). No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Introduce phb_ops->phb_final_fixup()Gavin Shan2016-05-031-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | phb_ops->device_node_fixup() was introduced for NPU1 so that the chip backend can bind the emulated NPU device with the GPU device and fixes the device-tree node accordingly. There're couple of issues as I can image: * In pci_fixup_nodes(), one PHB has only one level of device depth in the hierarchy tree. It's true for NPU PHBs, but false for other PHBs. That indicates the function can be called for NPU PHBs. * The callback name indicates the specific work to be done there. That doesn't make sense. We need another name without indicating the specific work to do. It will give the backend on chip level more freedom. Similarly, the callback is called on basis of PCI device. It's hard for backend to manuplate the PHB. More freedom the backend will get with more bold granularity. This fixes above issues by replacing phb_ops->device_node_fixup() with phb_ops->phb_final_fixup(). More freedom will be received in the backends. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Move PHB lock to generic layerGavin Shan2016-05-034-10/+12
| | | | | | | | | | | | | | | | All kinds of PHBs are maintaining a spinlock. At mean while, the spinlock is acquired or released by backends for phb_ops->lock() or phb_ops->unlock(). There're no difference of the logic on all kinds of PHBs. So it's reasonable to maintain the lock in the generic layer (struct phb). This moves lock from specific PHB to generic one. The spinlock is initialized when the generic PHB is registered in pci_register_phb(). Also, two inline functions phb_{lock, unlock}() are introduced to acquire/release it. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* chiptod: Sync timebase in both CAPP units on NaplesPhilippe Bergheaud2016-04-271-1/+2
| | | | | | | | | Naples has two capp units. In chiptod_capp_timebase_sync, call PHB3_CAPP_REG_OFFSET(p) to get the xscom register address offset, an operate on the right capp unit. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Load CAPP ucode to both CAPP units on NaplesPhilippe Bergheaud2016-04-273-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Venice and Murano have only one capp unit, that can be mapped to phb0, phb1 or phb2. Naples has two capp units, that are statically mapped, capp unit 0 on phb0 and capp unit 1 on phb1. The capp ucode must be loaded once onto each capp unit. This patch replaces the boolean chip->capp_ucode_loaded by a bitmap, and sets the bit corresponding to the phb index to indicate that ucode has been loaded. The macro CAPP_UCODE_LOADED(chip, phb) returns the value of the phb index bit. The xscom register addresses of capp unit 0 are identical to the register addresses of the single capp unit of Venice and Murano. The addresses of the Naples capp unit 1 are equal to the addresses of capp unit 0 + 0x180. This patch introduces the macro PHB3_CAPP_REG_OFFSET(p), that returns the following xscom register address offsets: 0x0 for the Venice capp unit 0x0 for the Murano capp unit 0x0 for Naples capp unit 0 0x180 for Naples capp unit 1 The offset is added to the register address at each xscom_write, in order to operate on the right capp unit. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Merge branch 'skiboot-5.2.x' - PHB3 raceStewart Smith2016-04-271-0/+2
|\
OpenPOWER on IntegriCloud