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* core/pci: Add phb->ops->device_removeGavin Shan2017-03-311-0/+1
| | | | | | | | | | This adds another PHB callback (device_remove()), corresponding to device_init(). With it, the PHB3 layer can receive notification upon PCI topology changes. This functionality will be used by the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Add init for power9 power managementAkshay Adiga2017-03-301-0/+6
| | | | | | | | | | | This patch adds new function to init core for power9 power management. SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each core during init. (This init are not required for MAMBO) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add hardware link training proceduresAlistair Popple2017-03-302-1/+15
| | | | | | | | | | Unlike other system buses the NVLink2 links need to be trained at runtime as training requires interaction from the GPU device drivers. This patch implements the required training procedures for NVLink2, which are different than the NVLink1 equivalents. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple2017-03-301-1/+4
| | | | | | | | | | | Adds three OPAL calls for interacting with NPU2 devices: opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar. These are used to setup and configure address translation services (ATS) for a process/partition on a given NVLink2 device. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Allocate GPU memory and describe it in the dtReza Arbab2017-03-301-0/+2
| | | | | | | | | | | | | Allocate memory for the GPU vidmem aperture and create "memory@" dt nodes to describe GPU memory with a phandle in each pointing to the emulated PCI device. Also provide the compressed 47-bit device address in "ibm,device-tgt-addr". Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Introduce NPU2 supportAlistair Popple2017-03-303-0/+154
| | | | | | | | | | | | | | | | | | NVLink2 is a new feature introduced on POWER9 systems. It is an evolution of of the NVLink1 feature included in POWER8+ systems but adds several new features including support for GPU address translation using the Nest MMU and cache coherence. Similar to NVLink1 the functionality is exposed to the OS as a series of virtual PCIe devices. However the actual hardware interfaces are significantly different which limits the amount of common code that can be shared between implementations in the firmware. This patch adds basic hardware initialisation and exposure of the virtual NVLink2 PCIe devices to the running OS. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add npu2 register definitionsAlistair Popple2017-03-301-0/+431
| | | | | | | | | NPU2 registers are split up into a series of stacks and blocks. This adds definitions and register offset calculation macros for all of the register stacks/blocks in preparation for NPU2. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Set max link speed via nvramMichael Neuling2017-03-291-0/+2
| | | | | | | | | | | | | This adds an nvram parameter pcie-max-link-speed to configure the max speed of the pcie link. This can be set from the petitboot prompt using: nvram -p ibm,skiboot --update-config pcie-max-link-speed=4 This takes preference over anything set in the device tree and is global to all PHBs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Add indirect form 1 scomsMichael Neuling2017-03-241-0/+1
| | | | | | | | | | | | | | Add code to perform indirect form 1 scoms. POWER8 does form 0 only. POWER9 adds form 1. The form is determined from the address only. Hardware only allows writes for form 1. Only hostboot uses these scoms during IPL, so they are unused by skiboot currently. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: disable CAPI mode during complete resetAndrew Donnellan2017-03-201-4/+5
| | | | | | | | | | | | | | | | | | | | When fast rebooting or kexec-ing a system with a PHB in CAPI mode, we need to return the PHB to regular PCIe mode. In order to do this, we have to reset a bunch of registers to their pre-CAPI-mode state. However, doing this while there is traffic going over the PCI link is dangerous and will generally cause a checkstop. As such, we want to do this while the PHB is fenced. Conveniently, during a complete reset we force a PHB fence, so this is a good opportunity to disable CAPI mode. When doing a complete reset, if the PHB is in CAPI mode, execute a sequence of SCOMs to reset PHB-related registers back to their regular, PCIe mode values. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt2017-03-161-0/+7
| | | | | | | | For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hmi: Print CAPP FIR information when handling CAPP malfunction alertsAndrew Donnellan2017-03-161-2/+5
| | | | | | | | | | | | | When diagnosing or debugging CAPP errors, it's rather useful to have the CAPP FIR, which often provides very helpful information. Print the CAPP FIR to the log when we handle a Malfunction Alert HMI for a CAPP error. Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/fsp: Do not queue SP and SPCN class messages during reset/reloadAnanth N Mavinakayanahalli2017-03-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | During FSP R/R, the FSP is inaccessible and will lose state. Messages to the FSP are generally queued for sending later. It does seem like the FSP fails to process any subseuqent messages of certain classes (SP info -- ipmi) if it receives queued mbox messages it isn't expecting. In certain other cases (sensors), the FSP driver returns a default code (async completion) even though there is no known bound from the time of this error return to the actual data being available. The kernel driver keeps waiting leading to soft-lockup on the host side. Mitigate both these (known) cases by returning OPAL_BUSY so the host driver knows to retry later. With this change, the sensors command works fine when the FSP comes back. This version also resolves the remaining IPMI issues Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Sync HW when moving interrupts aroundBenjamin Herrenschmidt2017-03-091-0/+7
| | | | | | | | For now sync all queues, ensure any interrupt routed at the old queue has reached memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdat: Parse BMC nodes much earlierOliver O'Halloran2017-03-071-0/+1
| | | | | | | | | | This moves the parsing of the BMC and LPC details to the start of the HDAT parsing. This allows us to enable the Skiboot log console earlier so we can get debug output while parsing the rest of the HDAT. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* System reset IPI facility and Mambo implementationNicholas Piggin2017-03-071-1/+2
| | | | | | | | | | | | | Add an opal call OPAL_SIGNAL_SYSTEM_RESET which allows system reset exceptions to be raised on other CPUs and act as an NMI IPI. There is an initial simple Mambo implementation, but allowances are made for a more complex hardware implementation. This API is based on the POWER8 implementation from Alistair Popple. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: minor RST fix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci/quirk: Populate device tree for AST2400 VGARussell Currey2017-03-031-0/+7
| | | | | | | | | | | | | | | | | Adding these properties enables the kernel to function in the same way that it would if it could no longer access BMC configuration registers through a backdoor, which may become the default in future. The comments describe how isolating the host from the BMC could be achieved in skiboot, assuming all kernels that the system boots support this. Isolating the BMC and the host from each other is important if they are owned by different parties; for example, a cloud provider renting machines "bare metal". Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Add a framework for quirksRussell Currey2017-03-031-0/+35
| | | | | | | | | | | | | | | | | | In future we may want to be able to do fixups for specific PCI devices in skiboot, so add a small framework for doing this. This is not intended for the same purposes as quirks in the Linux kernel, as the PCI devices that quirks can match for in skiboot are not properly configured. This is intended to enable having a custom path to make changes that don't directly interact with the PCI device, for example adding device tree entries. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: fix 0 vs NULL sparse warning, (C) date] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc/uart: Support routing of selected LPC interrupts to LinuxBenjamin Herrenschmidt2017-03-032-3/+6
| | | | | | | | | | | | | Each LPC interrupt can be routed to one of 4 lines to the PSI bridge which represent 4 different system interrupts. This allows LPC clients to request as specific target (Linux or OPAL) and makes the LPC core pick a route and configure it appropriately. The UART is updated to properly forward interrupts to Linux if necessary Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add some dump facilityBenjamin Herrenschmidt2017-02-231-2/+12
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* astbmc/pnor: Use mbox-flash for flash accessesCyril Bur2017-02-231-0/+1
| | | | | | | | | If the BMC is MBOX protocol aware, request flash reads/writes over the MBOX regs. This inits the blocklevel for pnor access with mbox-flash. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ast-bmc: Use the mbox driverCyril Bur2017-02-231-0/+3
| | | | | | | | | | | | The mbox registers are accessed via superIO, these need to be initialised. The mbox device node won't be present in the device tree hostboot passes us, so fixup the device tree. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/lpc-mbox: Add skiboot driver for the AST BMC mbox registersCyril Bur2017-02-232-0/+59
| | | | | | | | | This adds an internal skiboot API for accessing the AST BMC mbox registers. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Mark broken PDC on slots without surprise hotplug capabilityGavin Shan2017-02-221-0/+1
| | | | | | | | | | | | | | | | | We has to support surprise hotplug on PCI slots that don't support it on hardware. So we're fully utilizing the PCIe link state change event to detect the events (hot-remove and hot-add). The PDC (Presence Detection Change) event isn't reliable for the purpose. For example, PEX8718 on superMicro's machines. This adds another PCI slot property "ibm,slot-broken-pdc" in the device-tree, to indicate the PDC isn't reliable on those (software claimed) surprise pluggable slots. Reported-by: Hank Chang <hankmax0000@gmail.com> Signed-off-by: Gavin Shan <gwhsan@linux.vnet.ibm.com> Tested-by: Willie Liauw <williel@supermicro.com.tw> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* astbmc/p8dnu: Enable PCI slot's power supply on PEX9733 in hot-add pathGavin Shan2017-02-221-0/+1
| | | | | | | | | | | | | | | | | | | This issue is reported from superMicro's "p8dnu" platform. PEX9733 is connected to PHB direct slot. We create dynamic PCI slots for its (5) downstream ports and all of them support surprise hotplug capability. The problem is power supply lost on hot-remove and it isn't turned on automatically on hot-add. It means the PCIe link behind the slot isn't up and the PCI adapter behind the slot can't be probed successfully. This fixes the issue by forcing to turn on the power supply on hardware when user (kernel) requests to do so. Those PCI slots are identified by additional flag (PCI_SLOT_FLAG_FORCE_POWERON). Reported-by: Hank Chang <hankmax0000@gmail.com> Signed-off-by: Gavin Shan <gwhsan@linux.vnet.ibm.com> Tested-by: Willie Liauw <williel@supermicro.com.tw> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Fix PCIe slot's presenceGavin Shan2017-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to PCIe spec, the presence bit is hardcoded to 1 if PCIe switch downstream port doesn't support slot capability. The register used for the check in pcie_slot_get_presence_state() is wrong. It should be PCIe capability register instead of PCIe slot capability register. Otherwise, we always have present bit on the PCI topology. The issue is found on Supermicro's p8dtu2u machine: # lspci -t -+-[0022:00]---00.0-[01-08]----00.0-[02-08]--+-01.0-[03]----00.0 | \-02.0-[04-08]-- # cat /sys/bus/pci/slots/S002204/adapter 1 # lspci -vvs 0022:02:02.0 # lspci -vvs 0022:02:02.0 0022:02:02.0 PCI bridge: PLX Technology, Inc. PEX 8718 16-Lane, \ 5-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ab) (prog-if 00 [Normal decode]) : Capabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00 : SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- This fixes the issue by checking the correct register (PCIe capability). Also, the register's value is cached in advance as we did for slot and link capability. Fixes: bc66fb67aee ("core/pci: Support PCI slot") Cc: stable # 5.3.0+ Signed-off-by: Gavin Shan <gwhsan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Support SRIOV VFsGavin Shan2017-02-162-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, skiboot can't see SRIOV VFs. It introduces some troubles as I can see: The device initialization logic (phb->ops->device_init()) isn't applied to VFs, meaning we have to maintain same and duplicated mechanism in kernel for VFs only. It introduces difficulty to code maintaining and prone to lose sychronization. This was motivated by bug reported by Carol: The VF's Max Payload Size (MPS) isn't matched with PF's on Mellanox's adapter even kernel tried to make them same. It's caused by readonly PCIECAP_EXP_DEVCTL register on VFs. The skiboot would be best place to emulate this bits to eliminate the gap as I can see. This supports SRIOV VFs. When the PF's SRIOV capability is populated, the number of maximal VFs (struct pci_device) are instanciated, but but not usable yet. In the mean while, PCI config register filter is registered against PCIECAP_SRIOV_CTRL_VFE to capture the event of enabling or disabling VFs. The VFs are initialized, put into the PF's children list (pd->children), populate its PCI capabilities, and register PCI config register filter against PCICAP_EXP_DEVCTL. The filter's handler caches what is written to MPS field and returns the cached value on read, to eliminate the gap mentioned as above. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Allow associating parameter with capabilityGavin Shan2017-02-161-7/+20
| | | | | | | | | | When we start to support SRIOV capability in subsequent patches, a data struct will be instantiated and associated with the SRIOV capability. This extends the current implementation for that. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Introduce separate function to initialize PCIe capabilityGavin Shan2017-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | The logic initializing device's PCIe capability is resident in the function pci_scan_one() from day one. It's because information (e.g. vendor/device IDs) aren't stored into PCI device instance in old days. Now, the PCI device instance contains all information required to initialize its PCIe capability and others. This moves the logic initializing PCIe capability from pci_scan_one() to separate functions, pci_init_capabilities() and pci_init_pcie_cap(). pci_scan_one() is simplified to make code maintaining a bit easier. Also, it will allow us to intorduce separate functions to initialize other capabilities as we're doing for PCIe capability. This also exports pci_init_capabilities() so that it can be reused by SRIOV VFs in future. No logical changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt2017-02-072-0/+7
| | | | | | | | | | | | | | | | | On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* uart: Fix Linux pass-through policyBenjamin Herrenschmidt2017-02-071-2/+5
| | | | | | | | This was broken on Rhesus. Also add an nvram way of overriding the policy Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Initial support for the ELFv2 ABINicholas Piggin2017-02-061-0/+67
| | | | | | | | | | | | Provide an experimental option to compile using ELFv2 ABI even on big endian builds. ELFv2 + BE is not officially supported by the toolchain, but it works quite well. It may be useful as a small step toward a little-endian build. This saves about 200kB of text/data. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Grab P9 DD1.0 revision levelBenjamin Herrenschmidt2017-02-021-0/+1
| | | | | | | To differentiate between 1.00, 1.01, 1.02 etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTLBenjamin Herrenschmidt2017-02-021-0/+5
| | | | | | | | | This bits saves the day if the special EX BARs happens to be misconfigured. There is no drawback to having it always set so let's do so. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix definition of VC_SCRUB_OFFSETBenjamin Herrenschmidt2017-02-021-1/+1
| | | | | | | Off by one on one bit Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fix PIR mask for POWER9Michael Neuling2017-01-161-1/+1
| | | | | | | Fix typo in PIR mask for POWER9. Fixes booting multi-chip. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Reserve OPAL API numbers for XIVEStewart Smith2017-01-161-1/+5
| | | | | | (requested by benh) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vpd: add vpd_valid() to check keyword VPD blobsOliver O'Halloran2017-01-161-0/+2
| | | | | | | | | | Adds a function to check whether a blob is a valid IBM ASCII keyword VPD blob. This allows us to recognise when we do and do not have a VPD blob and act accordingly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: check if initial 0x84 exists. Spotted by Vasant] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dt: add dt_new_check()Oliver O'Halloran2017-01-151-0/+1
| | | | | | | | | | | | This is similar to dt_new(), but if the node already exists it will return the existing node. This is useful because some init code depends on the presence of certain nodes, but where the node is actually created is unimportant. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: add mprintf()Oliver O'Halloran2017-01-101-0/+2
| | | | | | | | | | mprintf() is printf(), but it goes straight to the mambo console. This allows it to be independent of Skiboot's actual console infrastructure so it can be used for debugging the console drivers and for debugging code that runs before the console is setup. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Add iterators for "present" CPUsBenjamin Herrenschmidt2017-01-051-0/+10
| | | | | | | | | Some code path want to look at all the CPUs that are "present", which means they have been enabled by HB/Cronus and can be accessed via XSCOMs, even if they haven't called in yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Split the OPAL irq flags from the internal onesBenjamin Herrenschmidt2017-01-051-5/+6
| | | | | | | | Some per-IRQ flags only have meaning inside OPAL, let's separate the two number spaces Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup escalation PQ on queue changeBenjamin Herrenschmidt2017-01-051-0/+4
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add *any chip* for allocating interruptsBenjamin Herrenschmidt2017-01-051-0/+5
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add support for EOIs via OPALBenjamin Herrenschmidt2017-01-051-0/+1
| | | | | | | | | | | opal_xive_eoi() can perform EOIs in XIVE exploitation mode as well as XICS emulation mode. Add a per-interrupt flag requiring the OS to use the OPAL call instead of ESB access. This is meant to be used as a broken HW workaround Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Work around broken LSI control on P9 DD1Benjamin Herrenschmidt2017-01-052-0/+2
| | | | | | | | | Exposes a new flag to the OS to indicate that OPAL calls are needed for masking and unmasking and forward the calls to the source so that PHB4 can do the right thing Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* interrupts: Add optional name for OPAL interruptsBenjamin Herrenschmidt2017-01-051-0/+4
| | | | | | | | | | | This adds the infrastructure for an interrupt source to provide a name for an interrupt directed toward OPAL. Those names will be put into an "opal-interrupts-names" property which is a standard DT string list corresponding 1:1 with the "opal-interrupts" property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Export opal_xive_reset() arguments in OPAL APIBenjamin Herrenschmidt2017-01-051-0/+9
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Implement xive_resetBenjamin Herrenschmidt2017-01-051-2/+4
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix build failure on older GCC - e.g. 4.8] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Mark XIVE owned EQs with a specific flagBenjamin Herrenschmidt2017-01-051-0/+2
| | | | | | | | This will allow us to recognize them later when doing a reset and avoid freeing them Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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