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* hw/phb3: Enable ECRC on endpointsGavin Shan2017-03-311-24/+2
| | | | | | | | | | | | As the ECRC is updated properly on root port, we needn't care the setting on endpoints. This reverts commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch"), meaning ECRC is always enabled on endpoints. Reported-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Adjust ECRC on root port dynamicallyGavin Shan2017-03-311-11/+63
| | | | | | | | | | | | | | | | | | | | | | | | | The issue was reported by Mark: the Samsung NVMe adapter is lost when it's connected to PMC 8546 PCIe switch, until ECRC is disabled on the root port. Actually, we found similar issue prevously when Broadcom adapter is connected to same part of PCIe switch and it was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch"). Unfortunately, the commit doesn't fix the Samsung NVMe adapter lost issue. This fixes the issues by disable ECRC generation/check on root port when PMC 8546 PCIe switch ports are found. This can be extended for other PCIe switches or endpoints in future: Each PHB maintains the count of PCI devices (PMC 8546 PCIe switch ports currently) which require to disable ECRC on root port. The ECRC functionality is enabled when first PMC 8546 switch port is probed and disabled when last PMC 8546 switch port is destroyed (in PCI hot remove scenario). Except PHB's reinitialization after complete reset, the ECRC on root port is untouched. Reported-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Add phb->ops->device_removeGavin Shan2017-03-313-0/+3
| | | | | | | | | | This adds another PHB callback (device_remove()), corresponding to device_init(). With it, the PHB3 layer can receive notification upon PCI topology changes. This functionality will be used by the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb4: Locate AER capability position if necessaryGavin Shan2017-03-311-6/+9
| | | | | | | | | | | | Similar to PHB3, phb4_init_rc_cfg() can be called when the PHB is initialized or reinitialized after complete reset. In the later case, we needn't locate the AER capability position again and the cached position can be used as we do for PCIe capability. So several CPU cycles can be saved. The error message is shortened and meaningless comment is dropped as well. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Locate AER capability position if necessaryGavin Shan2017-03-311-6/+9
| | | | | | | | | | | | phb3_init_rc_cfg() can be called when the PHB is initialized or reinitialized after complete reset. In the later case, we needn't locate the AER capability position again and the cached position can be used as we do for PCIe capability. So several CPU cycles can be saved. The error message is shortened and meaningless comment is dropped. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Add init for power9 power managementAkshay Adiga2017-03-301-7/+51
| | | | | | | | | | | This patch adds new function to init core for power9 power management. SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each core during init. (This init are not required for MAMBO) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add hardware link training proceduresAlistair Popple2017-03-303-3/+731
| | | | | | | | | | Unlike other system buses the NVLink2 links need to be trained at runtime as training requires interaction from the GPU device drivers. This patch implements the required training procedures for NVLink2, which are different than the NVLink1 equivalents. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple2017-03-301-1/+229
| | | | | | | | | | | Adds three OPAL calls for interacting with NPU2 devices: opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar. These are used to setup and configure address translation services (ATS) for a process/partition on a given NVLink2 device. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Allocate GPU memory and describe it in the dtReza Arbab2017-03-301-0/+196
| | | | | | | | | | | | | Allocate memory for the GPU vidmem aperture and create "memory@" dt nodes to describe GPU memory with a phandle in each pointing to the emulated PCI device. Also provide the compressed 47-bit device address in "ibm,device-tgt-addr". Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Introduce NPU2 supportAlistair Popple2017-03-302-1/+1389
| | | | | | | | | | | | | | | | | | NVLink2 is a new feature introduced on POWER9 systems. It is an evolution of of the NVLink1 feature included in POWER8+ systems but adds several new features including support for GPU address translation using the Nest MMU and cache coherence. Similar to NVLink1 the functionality is exposed to the OS as a series of virtual PCIe devices. However the actual hardware interfaces are significantly different which limits the amount of common code that can be shared between implementations in the firmware. This patch adds basic hardware initialisation and exposure of the virtual NVLink2 PCIe devices to the running OS. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Default to PCIe GEN2 on DD1Michael Neuling2017-03-291-1/+3
| | | | | | | | | Default to PCIe GEN2 link speeds on DD1 for stability. Can be overridden using nvram pcie-max-link-speed=4 parameter. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Set max link speed via nvramMichael Neuling2017-03-292-6/+28
| | | | | | | | | | | | | This adds an nvram parameter pcie-max-link-speed to configure the max speed of the pcie link. This can be set from the petitboot prompt using: nvram -p ibm,skiboot --update-config pcie-max-link-speed=4 This takes preference over anything set in the device tree and is global to all PHBs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Add indirect form 1 scomsMichael Neuling2017-03-241-2/+47
| | | | | | | | | | | | | | Add code to perform indirect form 1 scoms. POWER8 does form 0 only. POWER9 adds form 1. The form is determined from the address only. Hardware only allows writes for form 1. Only hostboot uses these scoms during IPL, so they are unused by skiboot currently. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Harden indirect writesMichael Neuling2017-03-241-0/+4
| | | | | | | | | Indirect scoms can only set certain bits of data. Ensure only these are set when trying to write. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Add POWER9 scom resetMichael Neuling2017-03-241-3/+9
| | | | | | | | Add scom reset registers for POWER9. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Abstract error recovery registersMichael Neuling2017-03-241-3/+9
| | | | | | | | Abstract error recovery registers to get ready for POWER9. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* homer : Enable HOMER region reservation for POWER9Shilpasri G Bhat2017-03-231-8/+74
| | | | | | | | | | PBA BARs map various regions in HOMER memory used by STOP engines and OCC. Skip PBA BARs that have incomplete initialization and reserve the regions that are available in the system. Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Define stop idle states for P9 DD1Shilpasri G Bhat2017-03-231-4/+57
| | | | | | | | | Only stop[0,1]_lite idle states are supported in DD1. And stop1 with ESL=EC=1 is used for CPU hotplug in DD1. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: add host sync notifier to trigger creset/CAPP disable on kexecAndrew Donnellan2017-03-201-0/+40
| | | | | | | | | | | | | | | | | | | | To support kexec in Linux, we need to trigger a creset to disable CAPP mode on each PHB that has been attached to a CAPP. Add a host sync notifier, phb3_host_sync_reset(), that will be triggered by the opal_sync_host_reboot() call that Linux makes when "shutting down" a powernv system (this includes bringing the system down to prepare it for kexec). This notifier will trigger a creset only on PHBs that need it, and will poll regularly until the creset completes. This approach is somewhat hacky, as it's somewhat of an abuse of the host sync notifier system (IMHO), but it seems the most obvious way to ensure that the reset/CAPP disable occurs that will work with old kernel versions and not require additional support on the kernel side. Suggested-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: disable CAPI mode during complete resetAndrew Donnellan2017-03-201-5/+136
| | | | | | | | | | | | | | | | | | | | When fast rebooting or kexec-ing a system with a PHB in CAPI mode, we need to return the PHB to regular PCIe mode. In order to do this, we have to reset a bunch of registers to their pre-CAPI-mode state. However, doing this while there is traffic going over the PCI link is dangerous and will generally cause a checkstop. As such, we want to do this while the PHB is fenced. Conveniently, during a complete reset we force a PHB fence, so this is a good opportunity to disable CAPI mode. When doing a complete reset, if the PHB is in CAPI mode, execute a sequence of SCOMs to reset PHB-related registers back to their regular, PCIe mode values. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc-mbox: Not existing is only an error on P9 and aboveStewart Smith2017-03-161-1/+5
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: fix NOTICE/WARNING of idle states found/not-foundStewart Smith2017-03-161-2/+2
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix typo in a commentBenjamin Herrenschmidt2017-03-161-1/+1
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Move xive_provision_cpu() aroundBenjamin Herrenschmidt2017-03-161-35/+35
| | | | | | | More logical organisation of the code. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Always reset queue state in opal_xive_set_queue_info()Benjamin Herrenschmidt2017-03-161-7/+13
| | | | | | | | | | | We used to require an enable/disable transition, however that doesn't work well with how KVM does "upgrade" a queue so instead just always reset the queue state (queue pointer and generation) whenever a queue is reconfigured. Escalations are reset to "masked" when the queue is disabled. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: When an interrupt is freed, also clear its enabled map entryBenjamin Herrenschmidt2017-03-161-0/+1
| | | | | | | Otherwise we try to disable an invalid IVE during xive_reset() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Remove some unnecessary debug outputBenjamin Herrenschmidt2017-03-161-5/+4
| | | | | | | .. and update a comment while at it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't reconfigure and enable queues and VPs in exploitationBenjamin Herrenschmidt2017-03-161-31/+56
| | | | | | | | | | | When the OS calls opal_xive_reset() to switch to exploitation mode, we shouldn't re-enable all the queues and VPs. The OS will do it. Otherwise, we miss the enable/disable transition, thus failing to re-initialize the queue count and generation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Refactor irq configurationBenjamin Herrenschmidt2017-03-161-77/+59
| | | | | | | | | Use a single common function for configuring an interrupt source that is called both by opal_set_xive() and opal_set_irq_configuration(), along with various internal users. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't expose a trigger page when none existBenjamin Herrenschmidt2017-03-161-5/+3
| | | | | | | | Otherwise Linux might try to retrigger an escalation interrupt when doing an EOI which will checkstop Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix recursive locking bug in opal_xive_reset()Benjamin Herrenschmidt2017-03-161-2/+3
| | | | | | | | | The re-initialization of the per-CPU data structures must be done without holding the xive lock as it will be taken when needed by the functions being called. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt2017-03-161-1/+46
| | | | | | | | For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't mess around with the ESB state when setting an IRQ configBenjamin Herrenschmidt2017-03-161-4/+10
| | | | | | | | | The host code needs to manage the ESB state in specific ways, it's not correct to blindly unmask the source when targetting for example, so let's not do that, the host will do it itself when appropriate. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: add support for p9 coresCédric Le Goater2017-03-161-0/+44
| | | | | | | | P9 cores have two DTS (the location unit is unknown to me for the moment) which have the same encoding than on the P8. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: introduce a dts_keep_max() routineCédric Le Goater2017-03-161-14/+19
| | | | | | | | This routine will also be used for reading the p9 core DTS and it saves a couple of lines in skiboot. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: remove unused definesCédric Le Goater2017-03-161-17/+6
| | | | | | | Also move the definitions closer to the code using them. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/fsp: Do not queue SP and SPCN class messages during reset/reloadAnanth N Mavinakayanahalli2017-03-163-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | During FSP R/R, the FSP is inaccessible and will lose state. Messages to the FSP are generally queued for sending later. It does seem like the FSP fails to process any subseuqent messages of certain classes (SP info -- ipmi) if it receives queued mbox messages it isn't expecting. In certain other cases (sensors), the FSP driver returns a default code (async completion) even though there is no known bound from the time of this error return to the actual data being available. The kernel driver keeps waiting leading to soft-lockup on the host side. Mitigate both these (known) cases by returning OPAL_BUSY so the host driver knows to retry later. With this change, the sensors command works fine when the FSP comes back. This version also resolves the remaining IPMI issues Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fsp-leds: add missing \n in duplicate loc code error msgStewart Smith2017-03-101-1/+1
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup calls to set_xive backendsBenjamin Herrenschmidt2017-03-091-6/+14
| | | | | | | | | | | | | | When interrupt sources provide a set_xive backend on P9 that means they have to do additional work to mask/unmask interrupts (typically due to issues in their ESB HW implementations). However, this never involves server targetting. Additionally there is confusion on what a "server number" means to a set_xive call due to the pre-P9 encoding, so let's not pass it at all, pass 0 instead. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Log the address of the boot time tablesBenjamin Herrenschmidt2017-03-091-0/+5
| | | | | | | This can be handy when debugging Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Sync HW when moving interrupts aroundBenjamin Herrenschmidt2017-03-091-1/+77
| | | | | | | | For now sync all queues, ensure any interrupt routed at the old queue has reached memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix setting of OPAL_XIVE_IRQ_EOI_VIA_FWBenjamin Herrenschmidt2017-03-091-4/+9
| | | | | | | | | | | This flag needs to be set when the original source has an EOI callback. It indicates that the OS should call back into OPAL to perform the EOI and is necessary for some LPC interrupts on DD1. Without this, Linux with XIVE exploitation hangs at boot with a stuck interrupt. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mbox: Sanitize init messageBenjamin Herrenschmidt2017-03-091-1/+3
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix xive reset corrupting EQ allocation bitmapBenjamin Herrenschmidt2017-03-091-6/+21
| | | | | | | | This causes us to hand out the physical processor EQs again to VPs when KVM uses the XIVE, thus causing loss of host interrupts. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdat: Parse BMC nodes much earlierOliver O'Halloran2017-03-071-0/+34
| | | | | | | | | | This moves the parsing of the BMC and LPC details to the start of the HDAT parsing. This allows us to enable the Skiboot log console earlier so we can get debug output while parsing the rest of the HDAT. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fixup init of struct lpc_clientStewart Smith2017-03-031-0/+3
| | | | | | | | | Gcc 4.8 would warn: hw/lpc-uart.c: In function 'uart_setup_os_passthrough': hw/lpc-uart.c:428:2: error: missing initializer for field 'reset' of 'struct lpc_client' [-Werror=missing-field-initializers] Fixes: a2940770ca6da2c58081f8207aded197e45f6cd6 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc/uart: Support routing of selected LPC interrupts to LinuxBenjamin Herrenschmidt2017-03-035-90/+201
| | | | | | | | | | | | | Each LPC interrupt can be routed to one of 4 lines to the PSI bridge which represent 4 different system interrupts. This allows LPC clients to request as specific target (Linux or OPAL) and makes the LPC core pick a route and configure it appropriately. The UART is updated to properly forward interrupts to Linux if necessary Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix TVE encoding for start addressFrederic Barrat2017-03-021-1/+1
| | | | | | | | | | | >From the phb4 spec, when encoding the TVE, the pci start address bits 49:24 are encoded in bits TVE[52:53]||[0:23]. The mask to select bits 47:24 is incorrectly set. It should be 0xffffff000000, shifted left by 16, i.e. 0xffffff << 40 Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: fix possible NULL dereferenceStewart Smith2017-03-021-2/+8
| | | | | | Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Always assign powerbus BARsBenjamin Herrenschmidt2017-02-231-0/+4
| | | | | | | | | | | HostBoot configure them with weird values that confuse us, instead let's just own the assignment. This is temporary, I will centralize memory map management next but this gets us going. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-By: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: Fixup commit message r.e. Mikey suggestion] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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