| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
If the BMC is MBOX protocol aware, request flash reads/writes over the
MBOX regs. This inits the blocklevel for pnor access with mbox-flash.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
The mbox registers are accessed via superIO, these need to be
initialised.
The mbox device node won't be present in the device tree hostboot passes
us, so fixup the device tree.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
This adds an internal skiboot API for accessing the AST BMC mbox
registers.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On boot, print the enabled stop states. Output looks like:
[ 25.045201661,5] SLW: Enabling: stop0_lite
[ 25.045205017,5] SLW: Enabling: stop0
[ 25.045206549,5] SLW: Enabling: stop1_lite
[ 25.045208320,5] SLW: Enabling: stop1
[ 25.045209738,5] SLW: Enabling: stop2_lite
[ 25.045211467,5] SLW: Enabling: stop2
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The PCI config register is applied before the HW register is changed.
It won't work when this mechanism is used to capture the change to
SRIOV capability in subsequent patch.
This moves the logic around so that the filter is applied after HW
register is changed. Currently, it's used to cache bridge's pref
window base/length. The code change shouldn't affect that. So no
functional changes introduced by this.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently, AER capability is initialized in phb_ops->device_init()
which is called after the device is instantiated by PCI core, or
reinitializing the device after reset in EEH recovery path. It
means we are maintaining similar sets of codes for P7IOC, PHB3
and PHB4.
This moves the logic initializing AER capability from P7IOC, PHB3
and PHB4 to PCI core, thus the duplicated codes can be dropped.
No functional changes introduced by this.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0,
we need an explicit clear after running the handler. (Not before
as they are level interrupts, they will be latched again if they
are still pending).
For now we do that in lpc_dispatch_ser_irqs() but that only works
for interrupts routed to OPAL.
In order to support routing LPC interrutps to Linux, we need a custom
EOI handler that does the clearing of the latch before we do the
EOI in the ESB.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
We support all the OPAL calls, and it avoids bugs in existing
Linux kernels that would otherwise crash when attempting to
access devices using a direct mapping.
When Linux is fixed it will recognize that direct mapping is
supported and avoid the OPAL calls.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
This was broken on Rhesus. Also add an nvram way of
overriding the policy
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Bits[0-15] are used to indicate the supported STOP states in
"ibm,enabled-stop-levels" DT property and STOP0 is starting from
Bit0. This patch fixes the parsing to read the appropriate bits.
Fixes: c3ea33f173ec ("hw/slw: only enable supported STOP states")
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
We have an typo in a @fwts-advice field, which means it's carried
through to the generated fwts olog data. This change fixes the typo so
that the advice output from fwts is correct.
CC: Deb McLemore <debmc@linux.vnet.ibm.com>
Reported-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Acked-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
SCOM doesn't exist, we end up in a sad place (machine check)
Fixes: c9cadb4fe60d4d41fc45a35a1d2ae27e0632c679
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
In case HostBoot leaves some gunk behind
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
To differentiate between 1.00, 1.01, 1.02 etc...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
There is a theorical possibility that if we don't get any
pending interrupt in the queue in opal_xive_get_xirr() due
to a spurious notification we leave the CPPR elevated.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Just use the one we know is valid rather than what's passed as
an argument. Linux might call us with 0.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
We were calculating the mask all wrong... we got lucky in the
normal case though.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
For the same reason as PHBs ... we need to move that to
a common module controlling the address map.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
This BAR is used to force a core to send "local" commands when hitting
the TM area which has the same address on all chips.
There is one copy of this per core *pair*. The existing code only sets
it up on core 0 of a pair. However some systems have core 1 and not
core 0 ... oooops.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
This helps debugging multi-chip problems
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
There are 4 snoopers, 0 and 3 are pretty busy, so let's use a mix
of 1 and 2 for the PHB and PSI notification ports. We do that by
using different cache line offsets. We use 1 for PHB0 which tends
to be the highest performance one and 2 for everybody else
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
This bits saves the day if the special EX BARs happens to
be misconfigured. There is no drawback to having it always
set so let's do so.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
After a scrub, use a sync to order any load to the newly updated
memory.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
Return an error instead
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
This patch adds parsing the ibm,enabled-stop-levels field when building
the /ibm,opal/power-mgt/ node so that only the STOP levels that have
been advertised by firmware are used.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
On P9 systems the /ibm,opal/power-mgt/ node may be created by the HDAT
parser before reaching add_cpu_idle_state_properties(). This is fine,
but it needs to be handled.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Adds support for parsing the PHB4 entries in the IOHUB array and
populating the devicetree appropriately.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[stewart@linux.vnet.ibm.com: s/DOUMO/DUOMO/, assert(), spotted by Vasant]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Fixes training at larger than PCIe Gen1 speeds.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
Add static to various declarations that can use it, as found by sparse.
It turns out that one of these (fsp_pcie_inv_lock in
platform/ibm-fsp/firenze.c) is actually unused, so remove it.
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Without this, not only backlog counters in groups aren't
incremented but IPB bits aren't set on unscheduled VPs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Otherwise, we try to access some XSCOMs on garded CPUs which
leads to all sorts of errors during boot.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
If we got a spurrious interrupt it would fail to bring the CPPR
back properly. Fix the logic to always adjust the CPPR and to
handle the absence of an interrupt correctly.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
We were using uninitialized memory for the VPs, causing occasionally
spurrious interrupts at startup due to IPB being non-0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
Don't try to play games with PQ bits with LSIs, use the normal EOI loads
instead as otherwise things won't work on P9 DD1 with PHB4 due to
erratas on all non-EOI ESB operations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Mask/unmask loses the information that the interrupt was sent to
the queue, thus fast mask/unmasks can potentially fill up the
queue with more than one copy of the same interrupt which is bad.
This will need to be fixed by remembering the need for an EOI
and restoring the interrupt accordingly on unmask
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
| |
We can do the Ack cycle using a simple load but we need a sync
before we look at the EQs, otherwise we might be missing the
EQ update corresponding to a priority in the ACK cycle.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
Otherwise we get warnings when masking interrupts
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Until the simulator is fixed, we need to use direct mode and
KVM loves allocating LOTs of VPs
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
| |
Otherwise get_xive/set_xive won't work
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Some per-IRQ flags only have meaning inside OPAL, let's separate
the two number spaces
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
Otherwise this can have the side effect of losing a queued
interrupt.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
There are two issues, first we didn't return a prio 0xff for a masked
IVE, second we shouldn't fail if the EQ isn't found as this can be called
for an interrupt that has never been routed to a valid EQ yet. In that
case, we pick a reasonable default server and a prio of 0xff.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
| |
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
| |
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
| |
These allocate blocks of VPs and corresponding EQDs,
and can unwind and report provisioning errors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|