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* xive: Add some dump facilityBenjamin Herrenschmidt2017-02-231-1/+129
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* astbmc/pnor: Use mbox-flash for flash accessesCyril Bur2017-02-231-0/+6
| | | | | | | | | If the BMC is MBOX protocol aware, request flash reads/writes over the MBOX regs. This inits the blocklevel for pnor access with mbox-flash. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ast-bmc: Use the mbox driverCyril Bur2017-02-231-0/+19
| | | | | | | | | | | | The mbox registers are accessed via superIO, these need to be initialised. The mbox device node won't be present in the device tree hostboot passes us, so fixup the device tree. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/lpc-mbox: Add skiboot driver for the AST BMC mbox registersCyril Bur2017-02-232-1/+281
| | | | | | | | | This adds an internal skiboot API for accessing the AST BMC mbox registers. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Print enabled stop statesMichael Neuling2017-02-221-0/+2
| | | | | | | | | | | | | | On boot, print the enabled stop states. Output looks like: [ 25.045201661,5] SLW: Enabling: stop0_lite [ 25.045205017,5] SLW: Enabling: stop0 [ 25.045206549,5] SLW: Enabling: stop1_lite [ 25.045208320,5] SLW: Enabling: stop1 [ 25.045209738,5] SLW: Enabling: stop2_lite [ 25.045211467,5] SLW: Enabling: stop2 Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Apply config register filter after HW changeGavin Shan2017-02-161-3/+3
| | | | | | | | | | | | | | | The PCI config register is applied before the HW register is changed. It won't work when this mechanism is used to capture the change to SRIOV capability in subsequent patch. This moves the logic around so that the filter is applied after HW register is changed. Currently, it's used to cache bridge's pref window base/length. The code change shouldn't affect that. So no functional changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Initialize AER capability in PCI coreGavin Shan2017-02-163-48/+9
| | | | | | | | | | | | | | | | Currently, AER capability is initialized in phb_ops->device_init() which is called after the device is instantiated by PCI core, or reinitializing the device after reset in EEH recovery path. It means we are maintaining similar sets of codes for P7IOC, PHB3 and PHB4. This moves the logic initializing AER capability from P7IOC, PHB3 and PHB4 to PCI core, thus the duplicated codes can be dropped. No functional changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt2017-02-073-6/+72
| | | | | | | | | | | | | | | | | On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Mark the power9 LPC bus as compatible with power8Benjamin Herrenschmidt2017-02-071-4/+8
| | | | | | | | | | | | We support all the OPAL calls, and it avoids bugs in existing Linux kernels that would otherwise crash when attempting to access devices using a direct mapping. When Linux is fixed it will recognize that direct mapping is supported and avoid the OPAL calls. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* uart: Fix Linux pass-through policyBenjamin Herrenschmidt2017-02-071-3/+34
| | | | | | | | This was broken on Rhesus. Also add an nvram way of overriding the policy Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Fix parsing of supported STOP statesShilpasri G Bhat2017-02-071-2/+4
| | | | | | | | | | | Bits[0-15] are used to indicate the supported STOP states in "ibm,enabled-stop-levels" DT property and STOP0 is starting from Bit0. This patch fixes the parsing to read the appropriate bits. Fixes: c3ea33f173ec ("hw/slw: only enable supported STOP states") Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: fix typo in slw dump commentJeremy Kerr2017-02-031-1/+1
| | | | | | | | | | | | We have an typo in a @fwts-advice field, which means it's carried through to the generated fwts olog data. This change fixes the typo so that the advice output from fwts is correct. CC: Deb McLemore <debmc@linux.vnet.ibm.com> Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Don't probe ECID for DD1.0X on MamboStewart Smith2017-02-031-1/+3
| | | | | | | SCOM doesn't exist, we end up in a sad place (machine check) Fixes: c9cadb4fe60d4d41fc45a35a1d2ae27e0632c679 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup TM area on CPU callingBenjamin Herrenschmidt2017-02-021-0/+8
| | | | | | | In case HostBoot leaves some gunk behind Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Grab P9 DD1.0 revision levelBenjamin Herrenschmidt2017-02-021-0/+28
| | | | | | | To differentiate between 1.00, 1.01, 1.02 etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix failure to lower CPPR in opal_xive_get_xirr()Benjamin Herrenschmidt2017-02-021-1/+7
| | | | | | | | | There is a theorical possibility that if we don't get any pending interrupt in the queue in opal_xive_get_xirr() due to a spurious notification we leave the CPPR elevated. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't assume opal_xive_eoi() is called with the right queue prioBenjamin Herrenschmidt2017-02-021-6/+3
| | | | | | | | Just use the one we know is valid rather than what's passed as an argument. Linux might call us with 0. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix opal_xive_check_pending()Benjamin Herrenschmidt2017-02-021-2/+2
| | | | | | | | We were calculating the mask all wrong... we got lucky in the normal case though. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Force assign BARsBenjamin Herrenschmidt2017-02-021-0/+4
| | | | | | | | For the same reason as PHBs ... we need to move that to a common module controlling the address map. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix configuration of the EX special BARBenjamin Herrenschmidt2017-02-021-19/+28
| | | | | | | | | | | | This BAR is used to force a core to send "local" commands when hitting the TM area which has the same address on all chips. There is one copy of this per core *pair*. The existing code only sets it up on core 0 of a pair. However some systems have core 1 and not core 0 ... oooops. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Display the block ID when initializing an instanceBenjamin Herrenschmidt2017-02-021-1/+1
| | | | | | | This helps debugging multi-chip problems Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Spread the notification ports a bitBenjamin Herrenschmidt2017-02-021-6/+8
| | | | | | | | | | There are 4 snoopers, 0 and 3 are pretty busy, so let's use a mix of 1 and 2 for the PHB and PSI notification ports. We do that by using different cache line offsets. We use 1 for PHB0 which tends to be the highest performance one and 2 for everybody else Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTLBenjamin Herrenschmidt2017-02-021-1/+1
| | | | | | | | | This bits saves the day if the special EX BARs happens to be misconfigured. There is no drawback to having it always set so let's do so. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Comments about in-memory overflow queuesBenjamin Herrenschmidt2017-02-021-0/+4
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cache scrub needs a syncBenjamin Herrenschmidt2017-02-021-0/+1
| | | | | | | | After a scrub, use a sync to order any load to the newly updated memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix PIR2VP_BLK for 2-chip systemsBenjamin Herrenschmidt2017-02-021-1/+10
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dts: Don't assert when we don't know the processor typeBenjamin Herrenschmidt2017-01-161-1/+1
| | | | | | | Return an error instead Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: only enable supported STOP statesOliver O'Halloran2017-01-161-0/+14
| | | | | | | | | This patch adds parsing the ibm,enabled-stop-levels field when building the /ibm,opal/power-mgt/ node so that only the STOP levels that have been advertised by firmware are used. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: use dt_new_check()Oliver O'Halloran2017-01-161-3/+2
| | | | | | | | | | On P9 systems the /ibm,opal/power-mgt/ node may be created by the HDAT parser before reaching add_cpu_idle_state_properties(). This is fine, but it needs to be handled. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdat: Add support for PHB4Oliver O'Halloran2017-01-151-2/+0
| | | | | | | | | Adds support for parsing the PHB4 entries in the IOHUB array and populating the devicetree appropriately. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: s/DOUMO/DUOMO/, assert(), spotted by Vasant] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix endian issue with link control2/status2 registersBenjamin Herrenschmidt2017-01-101-1/+1
| | | | | | | | Fixes training at larger than PCIe Gen1 speeds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* treewide: squash sparse static warningsAndrew Donnellan2017-01-052-2/+2
| | | | | | | | | | Add static to various declarations that can use it, as found by sparse. It turns out that one of these (fsp_pcie_inv_lock in platform/ibm-fsp/firenze.c) is actually unused, so remove it. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Enable backlog on queuesBenjamin Herrenschmidt2017-01-051-1/+1
| | | | | | | | Without this, not only backlog counters in groups aren't incremented but IPB bits aren't set on unscheduled VPs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Use for_each_present_cpu() for setting up XIVEBenjamin Herrenschmidt2017-01-051-4/+4
| | | | | | | | Otherwise, we try to access some XSCOMs on garded CPUs which leads to all sorts of errors during boot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix logic in opal_xive_get_xirr()Benjamin Herrenschmidt2017-01-051-9/+13
| | | | | | | | | If we got a spurrious interrupt it would fail to bring the CPPR back properly. Fix the logic to always adjust the CPPR and to handle the absence of an interrupt correctly. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Properly initialize new VP and EQ structuresBenjamin Herrenschmidt2017-01-051-0/+5
| | | | | | | | We were using uninitialized memory for the VPs, causing occasionally spurrious interrupts at startup due to IPB being non-0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Improve/fix EOI of LSIsBenjamin Herrenschmidt2017-01-051-12/+19
| | | | | | | | | Don't try to play games with PQ bits with LSIs, use the normal EOI loads instead as otherwise things won't work on P9 DD1 with PHB4 due to erratas on all non-EOI ESB operations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add FIXME comments about mask/umask racesBenjamin Herrenschmidt2017-01-051-0/+8
| | | | | | | | | | | | Mask/unmask loses the information that the interrupt was sent to the queue, thus fast mask/unmasks can potentially fill up the queue with more than one copy of the same interrupt which is bad. This will need to be fixed by remembering the need for an EOI and restoring the interrupt accordingly on unmask Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix memory barrier in opal_xive_get_xirr()Benjamin Herrenschmidt2017-01-051-2/+3
| | | | | | | | | We can do the Ack cycle using a simple load but we need a sync before we look at the EQs, otherwise we might be missing the EQ update corresponding to a priority in the ACK cycle. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't try to find a target EQ for prio 0xffBenjamin Herrenschmidt2017-01-051-12/+14
| | | | | | | Otherwise we get warnings when masking interrupts Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Bump table sizes in direct modeBenjamin Herrenschmidt2017-01-051-2/+2
| | | | | | | | Until the simulator is fixed, we need to use direct mode and KVM loves allocating LOTs of VPs Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Properly register escalation interruptsBenjamin Herrenschmidt2017-01-051-4/+13
| | | | | | | Otherwise get_xive/set_xive won't work Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Split the OPAL irq flags from the internal onesBenjamin Herrenschmidt2017-01-051-3/+21
| | | | | | | | Some per-IRQ flags only have meaning inside OPAL, let's separate the two number spaces Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't touch ESB masks unless masking/unmaskingBenjamin Herrenschmidt2017-01-051-6/+13
| | | | | | | | Otherwise this can have the side effect of losing a queued interrupt. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix xive_get_ir_targetting()Benjamin Herrenschmidt2017-01-051-11/+27
| | | | | | | | | | There are two issues, first we didn't return a prio 0xff for a masked IVE, second we shouldn't fail if the EQ isn't found as this can be called for an interrupt that has never been routed to a valid EQ yet. In that case, we pick a reasonable default server and a prio of 0xff. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup escalation PQ on queue changeBenjamin Herrenschmidt2017-01-051-4/+12
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add *any chip* for allocating interruptsBenjamin Herrenschmidt2017-01-051-1/+7
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add chip_id to get_vp_infoBenjamin Herrenschmidt2017-01-051-2/+7
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_get/set_vp_infoBenjamin Herrenschmidt2017-01-051-0/+97
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add VP alloc/free OPAL functionsBenjamin Herrenschmidt2017-01-051-12/+166
| | | | | | | | These allocate blocks of VPs and corresponding EQDs, and can unwind and report provisioning errors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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