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* xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt2017-07-121-38/+98
| | | | | | | | Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Remove historical BAR reading codeBenjamin Herrenschmidt2017-06-261-80/+11
| | | | | | | | | | We always use physmap to assign them, take out the code that tries to read and check the validity of the setup done by HB or cronus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: DD2.0 updatesBenjamin Herrenschmidt2017-06-261-8/+48
| | | | | | | | | Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page, and other cleanups Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix initialisation of xive_cpu_state structAndrew Donnellan2017-06-211-0/+1
| | | | | | | | | | | | | | When using XIVE emulation with DEBUG=1, we run into crashes in log_add() due to the xive_cpu_state->log_pos being uninitialised (and thus, with DEBUG enabled, initialised to the poison value of 0x99999999). Zero out the xive_cpu_state to fix this. Fixes: 6480d9656348 ("XIVE: Base XIVE support for OPAL XICS emulation calls") Reported-by: Alastair D'Silva <alastair@d-silva.org> Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran2017-06-161-7/+5
| | | | | | | | | | | | | | Currently we pass in a proc_chip structure to phys_map_get(). All we we really need from this structure is the Global Chip ID (GCID). This patch reworks the function so that we only need to pass the GCID which allows us to use it before the proc_chip structures have been initialised (i.e in the HDAT parser). Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-By: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Migrate BAR assignment to phys_map_get()Michael Neuling2017-05-101-30/+15
| | | | | | | Keeps existing addresses. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Workaround a problem with indirect TM accessBenjamin Herrenschmidt2017-05-031-0/+10
| | | | | | | | | | A HW issue can cause accesses to the content of the indirect data area to pass the actual selection of the target thread. The workaround is to read the PC_TCTXT_INDIR0 register back before accessing the data area. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Log more information in opal_xive_dump() for emulation stateBenjamin Herrenschmidt2017-05-011-4/+27
| | | | | | | | | | Add a counter of total interrupts taken by a CPU, dump the queue buffer both before and after the current pointer, and also display the HW state of the queue descriptor and the PQ state of the IPI. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add a per-cpu logging mechanism to XICS emulationBenjamin Herrenschmidt2017-05-011-1/+104
| | | | | | | | | This is a small 32-entries rolling buffer that logs a few operations. It's useful to debug odd problems. The output is printed when opal_xive_dump() is called. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Check queues for duplicates in DEBUG buildsBenjamin Herrenschmidt2017-05-011-1/+58
| | | | | | | | | | | There should never be duplicate interrupts in a queue. This adds code to check that when looking at the queue content. Since it can be a performance loss, this is only done for debug builds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive+phb4: Fix exposing trigger page to LinuxBenjamin Herrenschmidt2017-04-281-3/+12
| | | | | | | | | | | | | | | | | | | | | | We currently don't expose the trigger page of MSIs to Linux which breaks re-sending of a queued one. To fix that properly we need to understand out a subtle API complication: - The "internal" XIVE_SRC_TRIGGER_PAGE indicates that a trigger page is supported, whether it's the same page as the EOI page or not. - The "external" OPAL_XIVE_IRQ_TRIGGER_PAGE indicates that a *separate* trigger page exists. To know if triggers are supported the caller should simply check if a valid (non-0) value is returned in "out_trig_page" of opal_xive_get_irq_info(). So PHB4 must set XIVE_SRC_TRIGGER_PAGE for MSIs and the xive code needs to do the "right" thing for setting whether OPAL_XIVE_IRQ_TRIGGER_PAGE should be set or not. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix potential for lost IPIs when manipulating CPPRBenjamin Herrenschmidt2017-04-211-14/+19
| | | | | | | | | | | | | | We don't trigger the IPI in set_mfrr() if the CPPR of the destination is more favored than the MFRR. However, we fail to re-evaluate it when the CPPR later changes. This fixes it. The way this is implemented can lead to spurious IPIs but these are harmless. (Mikey remove bogus line setting xs->ipi_sent) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
* xive: Don't double EOI interrupts that have an EOI overrideBenjamin Herrenschmidt2017-04-211-2/+2
| | | | | | | | | | | | | Some interrupts source such as PSI serirq have a special EOI override. That override will perform the PQ bit EOI operation, so we must not do a second one in xive_source_eoi(). This bug can cause queue overflows, especially when dealing with runaway level interrupts. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
* xive: Clear emulation mode queue on resetBenjamin Herrenschmidt2017-04-191-0/+1
| | | | | | | | | | | | When resetting, we need to clear the emulation mode queue for each CPU, otherwise it may contain "stale" interrupts causing the OS to go completely out of sync. This fixes problems doing kexecs from emulation to native back to emulation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
* xive: Fixes/improvements to xive reset for multi-chip systemsBenjamin Herrenschmidt2017-04-191-19/+75
| | | | | | | | | | | | | | | | | On such systems, we really need to mask all the sources first, then synchronize all the XIVEs, before we start whacking their EQs, VPs etc... So this reworks the reset sequence to do that, using the new irq_for_each_source() iterator to get all the registered sources into a clean off state, and separating the sync pass from the reset pass. This also fixes a problem where the ipi_alloc_map wasn't being properly reset. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
* xive: Synchronize after disable IRQs in opal_xive_reset()Benjamin Herrenschmidt2017-04-191-0/+1
| | | | | | | | After all IRQs have been masked, sync the XIVE HW before we start disabling all the queues. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
* xive: Fix setting of remote NVT VSDBenjamin Herrenschmidt2017-04-051-1/+3
| | | | | | | | | | Unlike the other remote VSDs, the NVT one needs a valid size field that represents the size of the remote PC BAR. Without this, multi chip machines may checkstop when a processor pool or OS CAM gets attached to a VP on a different chip. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix typo in a commentBenjamin Herrenschmidt2017-03-161-1/+1
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Move xive_provision_cpu() aroundBenjamin Herrenschmidt2017-03-161-35/+35
| | | | | | | More logical organisation of the code. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Always reset queue state in opal_xive_set_queue_info()Benjamin Herrenschmidt2017-03-161-7/+13
| | | | | | | | | | | We used to require an enable/disable transition, however that doesn't work well with how KVM does "upgrade" a queue so instead just always reset the queue state (queue pointer and generation) whenever a queue is reconfigured. Escalations are reset to "masked" when the queue is disabled. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: When an interrupt is freed, also clear its enabled map entryBenjamin Herrenschmidt2017-03-161-0/+1
| | | | | | | Otherwise we try to disable an invalid IVE during xive_reset() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't reconfigure and enable queues and VPs in exploitationBenjamin Herrenschmidt2017-03-161-31/+56
| | | | | | | | | | | When the OS calls opal_xive_reset() to switch to exploitation mode, we shouldn't re-enable all the queues and VPs. The OS will do it. Otherwise, we miss the enable/disable transition, thus failing to re-initialize the queue count and generation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Refactor irq configurationBenjamin Herrenschmidt2017-03-161-77/+59
| | | | | | | | | Use a single common function for configuring an interrupt source that is called both by opal_set_xive() and opal_set_irq_configuration(), along with various internal users. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't expose a trigger page when none existBenjamin Herrenschmidt2017-03-161-5/+3
| | | | | | | | Otherwise Linux might try to retrigger an escalation interrupt when doing an EOI which will checkstop Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix recursive locking bug in opal_xive_reset()Benjamin Herrenschmidt2017-03-161-2/+3
| | | | | | | | | The re-initialization of the per-CPU data structures must be done without holding the xive lock as it will be taken when needed by the functions being called. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt2017-03-161-1/+46
| | | | | | | | For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't mess around with the ESB state when setting an IRQ configBenjamin Herrenschmidt2017-03-161-4/+10
| | | | | | | | | The host code needs to manage the ESB state in specific ways, it's not correct to blindly unmask the source when targetting for example, so let's not do that, the host will do it itself when appropriate. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup calls to set_xive backendsBenjamin Herrenschmidt2017-03-091-6/+14
| | | | | | | | | | | | | | When interrupt sources provide a set_xive backend on P9 that means they have to do additional work to mask/unmask interrupts (typically due to issues in their ESB HW implementations). However, this never involves server targetting. Additionally there is confusion on what a "server number" means to a set_xive call due to the pre-P9 encoding, so let's not pass it at all, pass 0 instead. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Log the address of the boot time tablesBenjamin Herrenschmidt2017-03-091-0/+5
| | | | | | | This can be handy when debugging Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Sync HW when moving interrupts aroundBenjamin Herrenschmidt2017-03-091-1/+77
| | | | | | | | For now sync all queues, ensure any interrupt routed at the old queue has reached memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix setting of OPAL_XIVE_IRQ_EOI_VIA_FWBenjamin Herrenschmidt2017-03-091-4/+9
| | | | | | | | | | | This flag needs to be set when the original source has an EOI callback. It indicates that the OS should call back into OPAL to perform the EOI and is necessary for some LPC interrupts on DD1. Without this, Linux with XIVE exploitation hangs at boot with a stuck interrupt. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix xive reset corrupting EQ allocation bitmapBenjamin Herrenschmidt2017-03-091-6/+21
| | | | | | | | This causes us to hand out the physical processor EQs again to VPs when KVM uses the XIVE, thus causing loss of host interrupts. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add some dump facilityBenjamin Herrenschmidt2017-02-231-1/+129
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt2017-02-071-1/+11
| | | | | | | | | | | | | | | | | On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup TM area on CPU callingBenjamin Herrenschmidt2017-02-021-0/+8
| | | | | | | In case HostBoot leaves some gunk behind Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix failure to lower CPPR in opal_xive_get_xirr()Benjamin Herrenschmidt2017-02-021-1/+7
| | | | | | | | | There is a theorical possibility that if we don't get any pending interrupt in the queue in opal_xive_get_xirr() due to a spurious notification we leave the CPPR elevated. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't assume opal_xive_eoi() is called with the right queue prioBenjamin Herrenschmidt2017-02-021-6/+3
| | | | | | | | Just use the one we know is valid rather than what's passed as an argument. Linux might call us with 0. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix opal_xive_check_pending()Benjamin Herrenschmidt2017-02-021-2/+2
| | | | | | | | We were calculating the mask all wrong... we got lucky in the normal case though. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Force assign BARsBenjamin Herrenschmidt2017-02-021-0/+4
| | | | | | | | For the same reason as PHBs ... we need to move that to a common module controlling the address map. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix configuration of the EX special BARBenjamin Herrenschmidt2017-02-021-19/+28
| | | | | | | | | | | | This BAR is used to force a core to send "local" commands when hitting the TM area which has the same address on all chips. There is one copy of this per core *pair*. The existing code only sets it up on core 0 of a pair. However some systems have core 1 and not core 0 ... oooops. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Display the block ID when initializing an instanceBenjamin Herrenschmidt2017-02-021-1/+1
| | | | | | | This helps debugging multi-chip problems Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Spread the notification ports a bitBenjamin Herrenschmidt2017-02-021-6/+8
| | | | | | | | | | There are 4 snoopers, 0 and 3 are pretty busy, so let's use a mix of 1 and 2 for the PHB and PSI notification ports. We do that by using different cache line offsets. We use 1 for PHB0 which tends to be the highest performance one and 2 for everybody else Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTLBenjamin Herrenschmidt2017-02-021-1/+1
| | | | | | | | | This bits saves the day if the special EX BARs happens to be misconfigured. There is no drawback to having it always set so let's do so. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Comments about in-memory overflow queuesBenjamin Herrenschmidt2017-02-021-0/+4
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cache scrub needs a syncBenjamin Herrenschmidt2017-02-021-0/+1
| | | | | | | | After a scrub, use a sync to order any load to the newly updated memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix PIR2VP_BLK for 2-chip systemsBenjamin Herrenschmidt2017-02-021-1/+10
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Enable backlog on queuesBenjamin Herrenschmidt2017-01-051-1/+1
| | | | | | | | Without this, not only backlog counters in groups aren't incremented but IPB bits aren't set on unscheduled VPs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Use for_each_present_cpu() for setting up XIVEBenjamin Herrenschmidt2017-01-051-4/+4
| | | | | | | | Otherwise, we try to access some XSCOMs on garded CPUs which leads to all sorts of errors during boot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix logic in opal_xive_get_xirr()Benjamin Herrenschmidt2017-01-051-9/+13
| | | | | | | | | If we got a spurrious interrupt it would fail to bring the CPPR back properly. Fix the logic to always adjust the CPPR and to handle the absence of an interrupt correctly. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Properly initialize new VP and EQ structuresBenjamin Herrenschmidt2017-01-051-0/+5
| | | | | | | | We were using uninitialized memory for the VPs, causing occasionally spurrious interrupts at startup due to IPB being non-0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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