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* xive: Improve/fix EOI of LSIsBenjamin Herrenschmidt2017-01-051-12/+19
| | | | | | | | | Don't try to play games with PQ bits with LSIs, use the normal EOI loads instead as otherwise things won't work on P9 DD1 with PHB4 due to erratas on all non-EOI ESB operations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add FIXME comments about mask/umask racesBenjamin Herrenschmidt2017-01-051-0/+8
| | | | | | | | | | | | Mask/unmask loses the information that the interrupt was sent to the queue, thus fast mask/unmasks can potentially fill up the queue with more than one copy of the same interrupt which is bad. This will need to be fixed by remembering the need for an EOI and restoring the interrupt accordingly on unmask Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix memory barrier in opal_xive_get_xirr()Benjamin Herrenschmidt2017-01-051-2/+3
| | | | | | | | | We can do the Ack cycle using a simple load but we need a sync before we look at the EQs, otherwise we might be missing the EQ update corresponding to a priority in the ACK cycle. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't try to find a target EQ for prio 0xffBenjamin Herrenschmidt2017-01-051-12/+14
| | | | | | | Otherwise we get warnings when masking interrupts Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Bump table sizes in direct modeBenjamin Herrenschmidt2017-01-051-2/+2
| | | | | | | | Until the simulator is fixed, we need to use direct mode and KVM loves allocating LOTs of VPs Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Properly register escalation interruptsBenjamin Herrenschmidt2017-01-051-4/+13
| | | | | | | Otherwise get_xive/set_xive won't work Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Split the OPAL irq flags from the internal onesBenjamin Herrenschmidt2017-01-051-3/+21
| | | | | | | | Some per-IRQ flags only have meaning inside OPAL, let's separate the two number spaces Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't touch ESB masks unless masking/unmaskingBenjamin Herrenschmidt2017-01-051-6/+13
| | | | | | | | Otherwise this can have the side effect of losing a queued interrupt. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Fix xive_get_ir_targetting()Benjamin Herrenschmidt2017-01-051-11/+27
| | | | | | | | | | There are two issues, first we didn't return a prio 0xff for a masked IVE, second we shouldn't fail if the EQ isn't found as this can be called for an interrupt that has never been routed to a valid EQ yet. In that case, we pick a reasonable default server and a prio of 0xff. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Cleanup escalation PQ on queue changeBenjamin Herrenschmidt2017-01-051-4/+12
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add *any chip* for allocating interruptsBenjamin Herrenschmidt2017-01-051-1/+7
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add chip_id to get_vp_infoBenjamin Herrenschmidt2017-01-051-2/+7
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_get/set_vp_infoBenjamin Herrenschmidt2017-01-051-0/+97
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add VP alloc/free OPAL functionsBenjamin Herrenschmidt2017-01-051-12/+166
| | | | | | | | These allocate blocks of VPs and corresponding EQDs, and can unwind and report provisioning errors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Workaround for bad DD1 checkerBenjamin Herrenschmidt2017-01-051-1/+5
| | | | | | | | | The VSD size for the EQDT/VPDT in the VC is badly checked by HW, we need to set it to all 1's (it never accesses the memory directly so the incorrect size doesn't matter) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add more checks for exploitation modeBenjamin Herrenschmidt2017-01-051-0/+14
| | | | | | | | All the exploitation mode APIs should return an error if the XIVE is configured for XICS emulation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add support for EOIs via OPALBenjamin Herrenschmidt2017-01-051-1/+13
| | | | | | | | | | | opal_xive_eoi() can perform EOIs in XIVE exploitation mode as well as XICS emulation mode. Add a per-interrupt flag requiring the OS to use the OPAL call instead of ESB access. This is meant to be used as a broken HW workaround Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Work around broken LSI control on P9 DD1Benjamin Herrenschmidt2017-01-051-4/+20
| | | | | | | | | Exposes a new flag to the OS to indicate that OPAL calls are needed for masking and unmasking and forward the calls to the source so that PHB4 can do the right thing Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Forward interrupt names callbackBenjamin Herrenschmidt2017-01-051-0/+10
| | | | | | | | The XIVE code wraps the interrupt sources, so we need to add a wrapper for the new "name" callback Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: eqgen isn't a booleanBenjamin Herrenschmidt2017-01-051-2/+2
| | | | | | | So don't treat it as such Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Export opal_xive_reset() arguments in OPAL APIBenjamin Herrenschmidt2017-01-051-3/+3
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add interrupt allocatorBenjamin Herrenschmidt2017-01-051-0/+110
| | | | | | | | This adds the OPAL calls for the OS to allocate and free new XIVE interrupts (aka IPIs). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Implement xive_resetBenjamin Herrenschmidt2017-01-051-10/+149
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix build failure on older GCC - e.g. 4.8] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Don't assert if xive_get_vp() failsBenjamin Herrenschmidt2017-01-051-1/+2
| | | | | | | Just return NULL to the caller Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Expose exploitation mode DT propertiesBenjamin Herrenschmidt2017-01-051-22/+60
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Use a constant for max# of chipsBenjamin Herrenschmidt2017-01-051-4/+4
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Keep track of which interrupts were ever enabledBenjamin Herrenschmidt2017-01-051-0/+14
| | | | | | | In order to speed up xive reset Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Implement internal VP allocatorBenjamin Herrenschmidt2017-01-051-39/+263
| | | | | | | | | | | We use a buddy allocator. A global one if block group mode is used, otherwise one per XIVE instance. It is not yet wired up to the OPAL APIs Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix bisect build breakage] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add xive_get/set_queue_infoBenjamin Herrenschmidt2017-01-051-0/+144
| | | | | | | This adds the two calls necessary to configure queues Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add helpers to encode and decode VP numbersBenjamin Herrenschmidt2017-01-051-5/+145
| | | | | | | | | | | The VP numbers passed to the OS are encoded in a specific way as to permit the use of HW PIR as valid VPs and as to encode the order of the VP allocation as part of the VP number. The encoding allows for the block group mode split blocks of VPs to still appear contiguous to the OS. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Change block numberingBenjamin Herrenschmidt2017-01-051-9/+6
| | | | | | | | | | Instead of making the block ID equal to the chip ID, we allocate block numbers in a linear way. This allows us to pack block numbers which will in turn give us a way to pick an aligned power of two set of block numbers for use by block group mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add API to donate pages in indirect modeBenjamin Herrenschmidt2017-01-051-2/+44
| | | | | | | | This allows the OS to donate pagess to XIVE for VP and EQ allocation Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add asynchronous cache updates and update irq targettingBenjamin Herrenschmidt2017-01-051-33/+49
| | | | | | | | | | | | xive_get/set_eq_info become xive_get/set_irq_targetting which can now return an error code. Add asynchronous cache watch. This returns OPAL_BUSY when the cache update hits a collision so that the retry is done by the caller. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Split xive_provision_cpu() and use cache watch for VPBenjamin Herrenschmidt2017-01-051-22/+57
| | | | | | | | | | | | | | This splits xive_provision_cpu() into one function that actually provisions the CPU by allocating the EQs and EQ page and will only be called once at boot, and a function that configures the default EQs and VPs and can be called potentially multiple times (such as from xive_reset). We also make the VP update use the cache watch rather than writing to the structure directly. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add cache scrub to push watch updates to memoryBenjamin Herrenschmidt2017-01-051-8/+14
| | | | | | | | | | We use the cache watch to write to some structures that we sometimes want to read back using normal loads. The cache watch facility only writes to the cache though, we need to add a non-invalidating cache scrub to also push the result to memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Mark XIVE owned EQs with a specific flagBenjamin Herrenschmidt2017-01-051-1/+2
| | | | | | | | This will allow us to recognize them later when doing a reset and avoid freeing them Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Use an allocator for EQDsBenjamin Herrenschmidt2017-01-051-85/+217
| | | | | | | | | | This adds a bitmap allocator for EQDs. They are allocated in groups of 8 naturally aligned. The VP structures associated with physical CPUs now have all 8 EQDs available though only one is provisioned and enabled. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Move xive_cpu_state up and clean up layoutBenjamin Herrenschmidt2017-01-051-26/+32
| | | | | | | | | | | | | This contains both fields used generally by XIVE for physical processors (including in exploitation mode) such as the reference to the physical VPs, and fields specific to the XICS emulation code. Make them separate and rename eqidx to eqptr as "idx" generally represent structure indices inside of VSDs and we are soon going to introduce an eq_idx field. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Remove obsolete INDIRECT_IS_LE workaroundsBenjamin Herrenschmidt2017-01-051-18/+0
| | | | | | | Simics has long been fixed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Break assumption that block ID == chip IDBenjamin Herrenschmidt2017-01-051-23/+62
| | | | | | | | | | Add proper translation between the two. We still initialize them to the same thing but we will be able to change that easily if necessary (if the chip IDs become larger than 16 or if we decide to start using more than one block per chip). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Handle bad ESB offsets in PHB4 DD1Benjamin Herrenschmidt2017-01-051-7/+16
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Implement get/set_irq_config APIsBenjamin Herrenschmidt2017-01-051-15/+59
| | | | | | | | They are almost identical to get/set_xive() with the addition of the logical irq number Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Rework xive_set_eq_info() to store all info even when maskingBenjamin Herrenschmidt2017-01-051-24/+22
| | | | | | | | | opal_get_xive() should return values set by opal_set_xive() for the server number even if the call was made with prio 0xff, so let's always store the proper values. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Implement cache watch and use it for EQsBenjamin Herrenschmidt2017-01-051-7/+99
| | | | | | | | We need to do cache coherent updates of the EQs when modifying escalation interrupts. Use the cache watch facility for that. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add locking to some API callsBenjamin Herrenschmidt2017-01-051-0/+13
| | | | | | | | | The interrupt allocation calls might happen from threaded inits and the EQ management can happen from Linux. The underlying cache management will require mutual exclusion. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_get_irq_info()Benjamin Herrenschmidt2017-01-051-0/+48
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add CPU node "interrupts" properties representing the IPIsBenjamin Herrenschmidt2017-01-051-0/+25
| | | | | | | | | This will be used in exploitation mode to request the IPIs for the various threads. Each core node has an "interrupts" property of the standard format for each thread of that core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add basic opal_xive_reset() call and exploitation modeBenjamin Herrenschmidt2017-01-051-0/+31
| | | | | | | | | | This adds an opal_xive_reset() call that currently does nothing other than store the mode (emulation vs. exploitation), and returns the appropriate error code if emulation mode calls are done while in exploitation mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add support for escalation interruptsBenjamin Herrenschmidt2017-01-051-35/+65
| | | | | | | | | | | | | | | Escalation interrupts have their "IVE" entry buried inside of the EQ that shoots them which complicates matters. We want to expose them to the OS as normal interrupts, so we dedicate a bit in the interrupt number (outside the range supported by the OPAL emulation API) to differenciate them. The BlockID and Index in the interrupt number now refer to the source EQ. This is still missing proper cache management for them, which will come in a separate patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Indirect table entries must have top bits "type" setBenjamin Herrenschmidt2016-11-151-0/+3
| | | | | | | | | The HW check that the 2 tops bits aren't both clear to differenciate an unallocated entry from a valid one. So we need to put some value there. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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