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* chip: Add simics specific quirksMichael Neuling2016-07-051-1/+2
| | | | | | | | | | Use that instead of mambo. Simics supports the F000F, so remove that quirk. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* flash: Use blocklevel to do ECC readsAlistair Popple2016-07-051-2/+2
| | | | | | | | | | | flash_read_corrected() assumes the passed blocklevel device is an actual flash device. However the blocklevel flash abstraction supports automatically reading ECC protected data so use that instead. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* flash: Increase the maximum number of flash devicesMichael Neuling2016-07-051-1/+1
| | | | | | | | | Increase the max number of flash devices from 1 to 8. With mambo bogusdisk, we can have many flash devices. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: supply ibm,dec-bits via devicetreeOliver O'Halloran2016-07-011-0/+48
| | | | | | | | | | | | | ISAv3 adds a mode to increase the size of the decrementer from 32 bits. The enlarged decrementer can be between 32 and 64 bits wide with the exact value being implementation dependent. This patch adds support for detecting the size of the large decrementer and populating each CPU node with the "ibm,dec-bits" property. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: rename enable_ld() to enable_large_dec()] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/opal.c: Add FWTS annotations for pollers and missing OPAL_CHECK_TOKENStewart Smith2016-06-271-2/+30
| | | | | | | | | | | | | | | For the missing OPAL_CHECK_TOKEN call, it means we catch kernel bugs in the firmware test suite, which I guess is a valid thing to do, if slightly odd. Unfortunately, kernels for POWER8 systems shipped with this (totally harmless) bug, so it's possible that if FWTS is run on older POWER8 PowerNV kernels, this warning will be hit. On POWER9 and above though, this warning should never be hit. The annotations for pollers should also never be hit, although I'm not convinced we don't have a spot or two in OPAL where this could still be the case (specifically, under certain error conditions). Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* i2c: Add FWTS annotations for I2c ErrorsStewart Smith2016-06-241-0/+13
| | | | | | | Two possible error states: kernel asks us for something incorrect, OPAL runs out of memory... both of which require investigation. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* nvlink: Print error message when NPU is fencedRussell Currey2016-06-211-1/+1
| | | | | | | | | | | | | | | NPU fences aren't recoverable, and as such, would require user intervention to have a working system again. The fence will be picked up by the kernel through EEH, but this doesn't happen until the NPU is used for something. So, let's print a message so it's obvious when this happens. A helper function was added to reduce duplication. This also enables code in skiboot to un-fence a NPU, which is useful to NPU developers but very stupid otherwise. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ccore/fflash.c: Ffix ttypo iin fflash eerror mmessageJeremy Kerr2016-06-201-1/+1
| | | | | | | wwhich -> which. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fwts: add annotations for core flash/nvram functionalityStewart Smith2016-06-201-0/+12
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add fwts annotations for critical errorsStewart Smith2016-06-203-0/+20
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Allow adding idle states to power-mgt node in mamboShreyas B. Prabhu2016-06-201-2/+1
| | | | | | | | | | | | | | | | | | | This patch removes the check which prevents adding any idle state to "power-mgt" node in mambo. Power8 exposes 3 idle states- nap, fast-sleep and deep-winkle. While fast-sleep depends on SCOMs and deep-winkle depends on SCOMs/SLW, nap has no such dependencies and it can be enabled in mambo. Current code checks for "fast-sleep" in hostboot provided "ibm,enabled-idle-states" dt node for adding fast-sleep and checks for presence of SLW for adding winkle to "power-mgt". Hence with this change only nap will be added to "power-mgt" node in mambo on Power8. On Power9, this patch enables all idle states which don't need SLW. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ATTN: Set attn bit instead of hile bit in enable/disable attn functionVasant Hegde2016-06-201-2/+2
| | | | | | | | | | | Commit 3ff35034 (Abstract HILE and attn enable bit definitions for HID0) enabled HILE bit instead of ATTN bit in enable/disable_attn fuction. Hence OPAL assert is failing. Fixes: 3ff35034 (Abstract HILE and attn enable bit definitions for HID0) CC: Michael Neuling <mikey@neuling.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/opal: Support PCI slot and new APIsGavin Shan2016-06-141-26/+209
| | | | | | | | | | | | | | | | | | | | | | | | | The various reset requests are completed by PHB's callbacks. All of them (except reset on IODA table or error injection) are covered by PCI slot. opal_pci_poll() faces similar situation. This reimplements opal_pci_reset() and opal_pci_poll() based on the callbacks provided by PCI slot instead of PHB. Also, couple of new APIs are introduced based on the callbacks in PCI slot as below: * opal_pci_get_presence_state(): Check if there is adapter presented behind the specified PHB or PCI slot. * opal_pci_get_power_state(): Returns power supply state (on or off) on the specified PHB or PCI slot. * opal_pci_set_power_state(): Sets power supply state (on or off) on the specified PHB or PCI slot. Besides, the state can be (offline or online) without changing the PCI slot's power state. Eventually, the definition of unused PHB's callbacks are removed. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Power off empty hotpluggable slotGavin Shan2016-06-141-1/+55
| | | | | | | | | | This powers off the empty hotpluggable slot during PCI enumeration for two purpose: power saving and initialize the slot to starting (power-off) state. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Use PCI slot in enumerationGavin Shan2016-06-141-141/+38
| | | | | | | | | | | | | | | | | | | | | | | | | During PCI enumeration, the root complex's link and fundamental reset are carried out by PHB's callbacks which are replaced by the corresponding PCI slot's callbacks. Also, the hotplug related device node properties are populated based on the PCI slot info that is included in PCI slot now. This uses PCI slot in enumeration: * Use PCI slot's callbacks for fundamental reset and link status retrieval in PCI enumeration. * Simplify the code by removing traditional PCI/PCI-x related logic as we don't have PCI/PCI-X root complex. * Replace pci_add_slot_properties() with pci_slot_add_properties() to populate PCI slot properties in device-tree. * PHB is always not hotpluggable. No hotpluggable properties in its device node are needed. * Remove "struct pci_slot_info" definition as its info is included in "struct pci_slot". Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Support PCI slotGavin Shan2016-06-144-25/+714
| | | | | | | | | | | | | | | | | | | Every PCIE bridge port or PHB is expected to be bound with PCI slot , to which various PCI slot's functionalities are attached (e.g. power, link, reset). This supports PCI slot: * PCI slot is reprsented by "struct pci_slot". * "struct pci_slot_ops" represents the functions supported on the PCI slot. It's initialized by PCI slot core at the beginning and allowed to be overrided by platform partially or completely. * On PCI hot plugging event, the PCI devices behind the slot are enumarated. Device sub-tree is populated and sent to OS by OPAL message. * On PCI hot unplugging event, the PCI devices behind the slot are destroyed. Device sub-tree is removed and the slot is powered off. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Return value for struct phb_ops::device_initGavin Shan2016-06-141-1/+1
| | | | | | | | | | This adds @data argument and "int" return value for struct phb_ops:: device_init() so that it can be called in pci_walk_dev() directly to reinitialize the PCI devices behind the specified slot in subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Extend pci_restore_bridge_buses() for PCI slotGavin Shan2016-06-141-2/+2
| | | | | | | | | | | | Currently, pci_restore_bridge_buses() restores the assigned bus ranges for all PCI bridges behind the specified PHB. This extends the function and allows doing same thing for the PCI bridges behind the specified slot. The extended functionality is going to be used by PCI hotplug logic in the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Extend pci_walk_dev() for PCI slotGavin Shan2016-06-141-4/+8
| | | | | | | | | | | Currently, pci_walk_dev() iterates all PCI devices behind the specified PHB. This extends the function to allow iteration on PCI devices behind the specified PCI slot so that it can be used by PCI hotplug logic in the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Fix wrong reserved PE# in enumerationGavin Shan2016-06-141-3/+12
| | | | | | | | | | | | | | | When scanning to non-existing PCI device, EEH (frozen) error is usually happening. We clear the unexpected frozen PE state after it. The reserved PE number is assumed to be 0 wrongly. So the frozen state on the reserved PE number isn't cleared properly. This introduces struct phb_ops::get_reserved_pe_number() to retrieve the reserved PE number from platforms. Then the EEH frozen state checking and clearing are applied to the reserved PE number. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/cpu: Introduce DEBUG_SERIALIZE_CPU_JOBSGavin Shan2016-06-141-0/+5
| | | | | | | | | | | | Currently, the PHB reset and PCI enumeration are done concurrently on multiple CPU cores. The output messages are interleaved and not readable enough. This adds a option to do the jobs in serialized fashion for debugging purpose only. The serialized mode should be always disabled in field. Suggested-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Introduce opal_get_device_tree()Gavin Shan2016-06-141-0/+40
| | | | | | | | | This introduces OPAL API opal_get_device_tree() to get the device sub-tree. It's going to be used in PCI hot add path. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Allow to exclude root nodeGavin Shan2016-06-142-12/+19
| | | | | | | | | | | | The root node is excluded in the device sub-tree created during PCI hot add time. This adds one extra argument @exclusive to flatten_dt_node(), __create_dtb() and create_dtb() to indicate the root node should be excluded or not. The changes are going to be used by PCI hot add path and it's not affecting anything at present. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Introduce __create_dtb()Gavin Shan2016-06-141-20/+24
| | | | | | | | | | | There is shared logic to flatten the whole device tree (used when loading kernel) or device sub-tree (used by PCI hot add). This introduces helper function __create_dtb() for the shared logic. No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Allow to specify FDT blobGavin Shan2016-06-141-20/+20
| | | | | | | | | | | | | | | | | There is a static variable @fdt pointing the FDT blob. The memory block is allocated by skiboot. After the device tree is flattened, it's passed to kernel when it's loaded. It works fine. The FDT blob for device sub-tree because of PCI hot add is allocated by kernel, using a static @fdt to dereferencing the FDT blob isn't correct any more. This adds @fdt argument to various functions to specify the target FDT blob memory block. As a result, the file scoped static variable @fdt is removed. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Introduce flatten_dt_properties()Gavin Shan2016-06-141-14/+13
| | | | | | | | | | | | | | | | We need unflatten the child nodes of the specified one during PCI hot add time. After it, the FDT blob is transferred to kernel and unflattened there. A device sub-tree is represented by the FDT blob and it excludes the specified (root) node. This introduces helper function flatten_dt_properties() to flatten the properties of the specified node. In the path to create the device sub-tree, the root's properties is skipped in subsequent patch. In the mean time, the node tag is created in flatten_dt_node() so that the function is self-contained. No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Improve debugging functionalityGavin Shan2016-06-141-19/+20
| | | | | | | | | | | | | This improves the debugging functionality in fdt.c. No functional changes introduced: * Replace printf() with prlog(). * Introduce FDT_DBG() which is enabled on DEBUG_FDT. * Move #ifdef before dump_fdt() for better extendability. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fixup whitespace and build warning/errorStewart Smith2016-06-091-4/+4
| | | | | Fixes: f46c1e506d199332b0f9741278c8ec35b3e39135 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Do a dummy config write to devices to establish bus numberBenjamin Herrenschmidt2016-06-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | On PCI Express, devices need to know their own bus number in order to provide the correct source identification (aka RID) in upstream packets they might send, such as error messages or DMAs. However while devices know (and hard wire) their own device and function number, they know nothing about bus numbers by default, those are decoded by bridges for routing. All they know is that if their parent bridge sends a "type 0" configuration access, they should decode it provided the device and function numbers match. The PCIe spec thus defines that when a device receive such a configuration access and it's a write, it should "capture" the bus number in the source field of the packet, and re-use as the originator bus number of all subsequent outgoing requests. In order to ensure that a device has this bus number firmly established before it's likely to send error packets upstream, we should thus do a dummy configuration write to it as soon as possible after probing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: fix Evolution broken patch, write vdid rather than &vdid as per Gavin suggestion] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdata: Make hdata_to_dt more suitable for fuzzingStewart Smith2016-05-181-5/+7
| | | | | | | | We make parse_hdat() return success/failure rather than assert. This allows the hdata_to_dt binary to gracefully error out rather than assert, which is useful when throwing it at a fuzzer. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add base POWER9 supportMichael Neuling2016-05-103-3/+23
| | | | | | | | | | | Add PVR detection, chip id and other misc bits for POWER9. POWER9 changes the location of the HILE and attn enable bits in the HID0 register, so add these definitions also. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: Fix Numbus typo, hdata_to_dt build fixes] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Abstract HILE and attn enable bit definitions for HID0Michael Neuling2016-05-101-4/+10
| | | | | | | | Abstract HILE and attn enable bits definitions for HID0 in case these locations randomly change in future chip revisions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Disable attn instruction on bootMichael Neuling2016-05-102-0/+18
| | | | | | | | | | | | Currently we don't touch the attn enable bit in HID0 on boot. When attn is enabled, it's available everywhere including HV=0. This is very dangerous for the host kernel. This explicitly disables the attn instruction on all CPUs on boot. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Remove mambo quirk in platform generic codeMichael Neuling2016-05-101-3/+0
| | | | | | | Mambo has it's own platform, so we can remove the generic hack. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Make trigger_attn() enable attn alsoMichael Neuling2016-05-101-0/+16
| | | | | | | | This changes trigger_attn() to also enable attn via HID0, so callers don't have to do it themselves. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Remove pci_put_phb()Gavin Shan2016-05-031-27/+0
| | | | | | | | | | | | | | pci_{get,put}_phb() were introduced to increase/decrease refcount or similar thing to PHB. They should show up in pairs and some code is obvious breaking the semantics, but the logic is good as pci_put_phb() does nothing. As we do not maintain refcount for PHB and we should not have PHB unplugging in near future, it simply drops pci_put_phb(). No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Introduce phb_ops->phb_final_fixup()Gavin Shan2016-05-031-15/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | phb_ops->device_node_fixup() was introduced for NPU1 so that the chip backend can bind the emulated NPU device with the GPU device and fixes the device-tree node accordingly. There're couple of issues as I can image: * In pci_fixup_nodes(), one PHB has only one level of device depth in the hierarchy tree. It's true for NPU PHBs, but false for other PHBs. That indicates the function can be called for NPU PHBs. * The callback name indicates the specific work to be done there. That doesn't make sense. We need another name without indicating the specific work to do. It will give the backend on chip level more freedom. Similarly, the callback is called on basis of PCI device. It's hard for backend to manuplate the PHB. More freedom the backend will get with more bold granularity. This fixes above issues by replacing phb_ops->device_node_fixup() with phb_ops->phb_final_fixup(). More freedom will be received in the backends. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* PCI: Move PHB lock to generic layerGavin Shan2016-05-033-60/+59
| | | | | | | | | | | | | | | | All kinds of PHBs are maintaining a spinlock. At mean while, the spinlock is acquired or released by backends for phb_ops->lock() or phb_ops->unlock(). There're no difference of the logic on all kinds of PHBs. So it's reasonable to maintain the lock in the generic layer (struct phb). This moves lock from specific PHB to generic one. The spinlock is initialized when the generic PHB is registered in pci_register_phb(). Also, two inline functions phb_{lock, unlock}() are introduced to acquire/release it. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/flash: Add fwts olog annotationsJeremy Kerr2016-04-281-0/+20
| | | | | | | | This change adds a few fwts patterns to the flash code, mostly as an example of the annotations we have. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hmi: Recover both CAPP units on Naples after malfunction alertPhilippe Bergheaud2016-04-271-12/+35
| | | | | | | | Naples has two capp units. Probe both units to identify the card in error. Use the xscom register offset to operate on the right unit. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Merge branch 'skiboot-5.2.x' - partial HMIStewart Smith2016-04-011-7/+8
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| * Merge branch 'skiboot-5.1.x' into skiboot-5.2.x - partial HMI fixStewart Smith2016-04-011-7/+8
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| | * hmi: Fix a bug where partial hmi event was reported to host.Mahesh Salgaonkar2016-04-011-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code sends partial hmi event (4 * 64bits instead of 5 * 64bits) to host. The last 64 bits contains chip id/pir info for reporting checkstop events. This bug affects only checkstop events. Host console o/p without this patch: [ 305.628283] Fatal Hypervisor Maintenance interrupt [Not recovered] [ 305.628341] Error detail: Malfunction Alert [ 305.628388] HMER: 8040000000000000 [ 305.628423] CPU PIR: 00000000 [ 305.628458] [Unit: VSU] Logic core check stop Host console o/p with this patch: [ 200.122883] Fatal Hypervisor Maintenance interrupt [Not recovered] [ 200.122941] Error detail: Malfunction Alert [ 200.122986] HMER: 8040000000000000 [ 200.123021] CPU PIR: 000008e8 [ 200.123055] [Unit: VSU] Logic core check stop Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | | opal/errorlog :Removes the two times inclusion of header file errorlog.h ↵Mukesh Ojha2016-04-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from errorlog.c Removes two times inclusion of the same header file errorlog.h inside errorlog.c Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | | core/fdt: Adjust parameter for dt_{property, begin_node}Gavin Shan2016-03-311-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This passes property and device node as parameter to dt_property() and dt_begin_node separately so that we don't have to pass the individual fields of those two structs to the functions. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | | Merge branch 'skiboot-5.2.x' - NPU checkstopStewart Smith2016-03-312-12/+96
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| * | hmi: Add handling for NPU checkstopsRussell Currey2016-03-311-1/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the NPU detects an unrecoverable error, it will send a HMI. This is problematic since unhandled HMIs will checkstop the entire system, which is not the intended behaviour of a NPU failure. Instead, the NPU emulated PCI devices should be fenced as part of EEH. Add support for handling NPU HMIs. This works by finding the NPU responsible for the HMI, checking its error registers, and sending a recoverable HMI event. The NPU itself cannot actually recover, but the system should not be brought down. Fence mode is set on the NPU, such that any further operations on the NPU will trigger EEH, and it will be subsequently fenced from the system. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * | hmi: Only raise a catchall HMI if no other components haveRussell Currey2016-03-311-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regardless of whether a handler for a specific component has raised an event to deal with a HMI or not, skiboot will raise an extra HMI at the end of the detection. This is problematic, as if one component reports it is recoverable but another reports it is not, the last handler to be called will have priority. Rework this to instead only send a HMI event if no handler has raised an event themselves. This will send an unknown, unrecoverable HMI event since the cause could not be found. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * | hmi: Rework HMI event handling of FIR read failureRussell Currey2016-03-311-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If reading the FIR with XSCOM failed, the existing code would not raise a HMI under the assumption that the CPU was asleep and nothing is wrong. Now that it is possible to check whether or not the CPU was asleep, raise an unrecoverable HMI if the read failed for other reasons, and skip the CPU if it was asleep. If the CPU is asleep when it's not meant to be and that is the cause of the HMI, an unrecoverable "catchall" HMI will be raised since no other components will claim responsibility for it. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| * | hmi: Fix incorrect error messageRussell Currey2016-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An error message was clearly copy-pasted from the register beforehand, so fix. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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