Fix for typos

While reviewing the Debian packaging, codespell found those.
Most proposed fixes are based on codespell's default dictionnary.

Signed-off-by: Frederic Bonnard <frediz@linux.vnet.ibm.com>
Reviewed-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

6 files changed, 14 insertions, 14 deletions

diff --git a/libpore/p8_pore_table_gen_api_fixed.C b/libpore/p8_pore_table_gen_api_fixed.C
index 60c0679d..3163bc97 100644
--- a/libpore/p8_pore_table_gen_api_fixed.C
+++ b/libpore/p8_pore_table_gen_api_fixed.C
@@ -715,7 +715,7 @@ uint32_t p8_pore_gen_scom_fixed(void       *io_image,
   //   except the APPEND command, incl the translated REPLACE->APPEND, which will result 
   //   in the previously mentioned code error being returned.
   // - The table can be full but still include NOOPs. If so, we can still APPEND since
-  //   we append at first occurrance of a NOOP or at the end of the table (at the RET).
+  //   we append at first occurrence of a NOOP or at the end of the table (at the RET).
   switch (i_section)  {
   case P8_SCOM_SECTION_NC:
     if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_NC) &&
diff --git a/libpore/pgas.h b/libpore/pgas.h
index 3d985f80..5d1dbf38 100644
--- a/libpore/pgas.h
+++ b/libpore/pgas.h
@@ -34,7 +34,7 @@
 /// \file pgas.h
 /// \brief Pore GAS
 ///
-/// PGAS is documented in a seperate standalone document entitled <em> PGAS :
+/// PGAS is documented in a separate standalone document entitled <em> PGAS :
 /// PORE GAS (GNU Assembler) User's and Reference Manual </em>.
 ///
 /// This file defines support macros for the GNU PORE assembler, and the PORE
@@ -600,7 +600,7 @@
         // HW274735 documents that BC and BS are broken for the PORE-GPE0/1
         // pair. This bug is unfixed in POWER8, and by default we require BSI
         // and BCI to be implemented as macros on all engines. For
-        // compatability we continue to require that dx == D0.
+        // compatibility we continue to require that dx == D0.
 
         .macro  bsi, dx:req, offset:req, base:req, imm:req
         ..d0    (\dx)
diff --git a/libpore/pore_inline.h b/libpore/pore_inline.h
index f74aa6fa..214fca6f 100644
--- a/libpore/pore_inline.h
+++ b/libpore/pore_inline.h
@@ -291,7 +291,7 @@ typedef uint32_t PoreInlineLocation;
 /// PORE inline assembler context
 ///
 /// See the documentation page \ref pore_inline_assembler and the function
-/// pore_inline_context_create() for futher details.
+/// pore_inline_context_create() for further details.
 
 typedef struct {
 
diff --git a/libpore/pore_inline_assembler.c b/libpore/pore_inline_assembler.c
index 44a93db8..6c8e303e 100644
--- a/libpore/pore_inline_assembler.c
+++ b/libpore/pore_inline_assembler.c
@@ -108,7 +108,7 @@
 /// 
 /// Since the PORE instruction APIs are effectivly predicates, linear code
 /// sequences are easily assembled using the C-language logical OR construct.
-/// Any non-0 return code will immediatly break the sequence and set the
+/// Any non-0 return code will immediately break the sequence and set the
 /// expression value to 1.  The failure code can then be recovered from the \a
 /// error field of the context.  This coding technique is illustrated in the
 /// following example of assembling a memory-memory copy sequence.
@@ -890,7 +890,7 @@ pore_inline_instruction3(PoreInlineContext *ctx, int opcode, uint32_t operand,
 // Assemble WAIT
 //
 // The cycle count must be an unsigned 24-bit immediate otherwise the error
-// PORE_INLINE_UINT24_REQUIRED is signalled.  PGAS requires that HALT be used
+// PORE_INLINE_UINT24_REQUIRED is signaled.  PGAS requires that HALT be used
 // if the intention is to halt 
 
 int
@@ -914,7 +914,7 @@ pore_WAITS(PoreInlineContext *ctx, uint32_t cycles)
 // Assemble HOOKI
 //
 // The hook index must be an unsigned 24-bit immediate otherwise the error
-// PORE_INLINE_UINT24_REQUIRED is signalled.
+// PORE_INLINE_UINT24_REQUIRED is signaled.
 
 int
 pore_HOOKI(PoreInlineContext *ctx, uint32_t index, uint64_t imm)
diff --git a/libpore/sbe_xip_image.c b/libpore/sbe_xip_image.c
index 7ee48864..3f32d653 100644
--- a/libpore/sbe_xip_image.c
+++ b/libpore/sbe_xip_image.c
@@ -906,7 +906,7 @@ xipValidateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg)
 // "FNV hash algorithms and source code have been released into the public
 // domain. The authors of the FNV algorithmm look deliberate steps to disclose
 // the algorhtm (sic) in a public forum soon after it was invented. More than
-// a year passed after this public disclosure and the authors deliberatly took
+// a year passed after this public disclosure and the authors deliberately took
 // no steps to patent the FNV algorithm. Therefore it is safe to say that the
 // FNV authors have no patent claims on the FNV algorithm as published."
 
diff --git a/libpore/sbe_xip_image.h b/libpore/sbe_xip_image.h
index 8ba55b4a..955f3dcf 100644
--- a/libpore/sbe_xip_image.h
+++ b/libpore/sbe_xip_image.h
@@ -215,7 +215,7 @@
 /// Final alignment constraint for SBE-XIP images.
 ///
 /// PORE images are required to be multiples of 8 bytes in length, to
-/// gaurantee that the PoreVe will be able to complete any 8-byte load/store.
+/// guarantee that the PoreVe will be able to complete any 8-byte load/store.
 #define SBE_XIP_FINAL_ALIGNMENT 8
 
 
@@ -270,7 +270,7 @@ typedef struct {
     /// unaligned instruction or data fetches.  Some sections and subsections
     /// must also be POWER cache-line aligned. The \a iv_alignment applies to
     /// the first byte of the section. PORE images are also required to be
-    /// multiples of 8 bytes in length, to gaurantee that the PoreVe will be
+    /// multiples of 8 bytes in length, to guarantee that the PoreVe will be
     /// able to complete any 8-byte load/store.  These constraints are checked
     /// by sbe_xip_validate() and enforced by sbe_xip_append(). The alignment
     /// constraints may force a section to be padded, which may create "holes"
@@ -811,7 +811,7 @@ sbe_xip_get_string(void *i_image, const char* i_id, char** o_data);
 /// images in terms of their relocatable PORE addresses.  The API checks that
 /// the \a i_poreAddress is properly aligned and contained in the image, then
 /// reads the contents of \a i_poreAddress into \a o_data, performing
-/// image-to-host endianess conversion if required.
+/// image-to-host endianness conversion if required.
 ///
 /// \retval 0 Success
 ///
@@ -926,7 +926,7 @@ sbe_xip_set_string(void *io_image, const char* i_id, const char* i_data);
 /// images in terms of their relocatable PORE addresses.  The API checks that
 /// the \a i_poreAddress is properly aligned and contained in the image, then
 /// updates the contents of \a i_poreAddress with \a i_data, performing
-/// host-to-image endianess conversion if required.
+/// host-to-image endianness conversion if required.
 ///
 /// \retval 0 Success
 ///
@@ -1332,7 +1332,7 @@ sbe_xip_pore2section(const void* i_image,
 /// \param[in] i_hostAddress A host address addressing data within the image.
 ///
 /// \param[out] o_poreAddress The API updates the location pointed to by \a
-/// o_poreAddress with the equivelent relocatable PORE address of the memory
+/// o_poreAddress with the equivalent relocatable PORE address of the memory
 /// addressed by i_hostAddress.  Since valid PORE addresses are always either
 /// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
 /// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the PORE
@@ -1416,7 +1416,7 @@ sbe_xip_host2pore(const void* i_image,
 /// Attempt to grow the image past its defined memory allocation
 #define SBE_XIP_WOULD_OVERFLOW 14
 
-/// Error associated with the disassembler occured.
+/// Error associated with the disassembler occurred.
 #define SBE_XIP_DISASSEMBLER_ERROR 15
 
 /// hash collision creating the .fixed_toc section