diff options
| author | Cyril Bur <cyril.bur@au1.ibm.com> | 2017-05-24 16:37:17 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-05-26 15:55:23 +1000 |
| commit | 0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7 (patch) | |
| tree | 6f2625adc7db89fb61a06ec814ea4699915d3787 /libflash/mbox-flash.c | |
| parent | cc40ffb3a20f02ae968cebc9a0f0af8e8825bfb3 (diff) | |
| download | talos-skiboot-0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7.tar.gz talos-skiboot-0322cd881ab3fda2b8136d6beb3991fd9d2dc5e7.zip | |
hw/lpc-mbox: Use message registers for interrupts
Currently the BMC raises the interrupt using the BMC control register.
It does so on all accesses to the 16 'data' registers meaning that when
the BMC only wants to set the ATTN (on which we have interrupts enabled)
bit we will also get a control register based interrupt.
The solution here is to mask that interrupt permanantly and enable
interrupts on the protocol defined 'response' data byte.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'libflash/mbox-flash.c')
0 files changed, 0 insertions, 0 deletions
