diff options
| author | Andrew Donnellan <andrew.donnellan@au1.ibm.com> | 2018-03-01 18:57:15 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-03-01 20:17:54 -0600 |
| commit | 6b1cdedcef1d3aa0b4eb772228b5c5aad24764dc (patch) | |
| tree | 5c3b4ab25352cd8b05fb763f867c34cf61ee0d8c /include | |
| parent | 9db58b1e5c031782c442f92775ee75326a7be1b3 (diff) | |
| download | talos-skiboot-6b1cdedcef1d3aa0b4eb772228b5c5aad24764dc.tar.gz talos-skiboot-6b1cdedcef1d3aa0b4eb772228b5c5aad24764dc.zip | |
npu2-opencapi: Train OpenCAPI links and setup devices
Scan the OpenCAPI links under the NPU, and for each link, reset the card,
set up a device, train the link and register a PHB.
Implement the necessary operations for the OpenCAPI PHB type.
For bringup, test and debug purposes, we allow an NVRAM setting,
"opencapi-link-training" that can be set to either disable link training
completely or to use the prbs31 test pattern.
To disable link training:
nvram -p ibm,skiboot --update-config opencapi-link-training=none
To use prbs31:
nvram -p ibm,skiboot --update-config opencapi-link-training=prbs31
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu2-regs.h | 52 | ||||
| -rw-r--r-- | include/npu2.h | 7 |
2 files changed, 57 insertions, 2 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 7ef5994f..faaf5a17 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -122,6 +122,7 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_CQ_SM_MISC_CFG0_CONFIG_ENABLE_PBUS PPC_BIT(38) #define NPU2_CQ_SM_MISC_CFG0_CONFIG_OCAPI_MODE PPC_BIT(57) #define NPU2_CQ_SM_MISC_CFG1 0x008 +#define NPU2_CQ_SM_MISC_CFG2 0x148 #define NPU2_PB_EPSILON 0x010 #define NPU2_TIMER_CFG 0x018 #define NPU2_GPU0_MEM_BAR 0x020 @@ -193,7 +194,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_CQ_CTL_MISC_CFG_CONFIG_OCAPI_MODE PPC_BIT(52) #define NPU2_CQ_CTL_MISC_CFG_CONFIG_OTL0_ENABLE PPC_BIT(55) #define NPU2_CQ_CTL_MISC_CFG_CONFIG_OTL1_ENABLE PPC_BIT(56) -#define NPU2_CQ_FUTURE_CFG1 0x008 +#define NPU2_CQ_CTL_MISC_MMIOPA0_CONFIG 0x0B0 +#define NPU2_CQ_CTL_MISC_MMIOPA_ADDR PPC_BITMASK(1,35) +#define NPU2_CQ_CTL_MISC_MMIOPA_SIZE PPC_BITMASK(39,43) +#define NPU2_CQ_CTL_MISC_MMIOPA1_CONFIG 0x0B8 +#define NPU2_CQ_CTL_MISC_CFG1 0x008 #define NPU2_CQ_FUTURE_CFG2 0x010 #define NPU2_CQ_FUTURE_CFG3 0x018 #define NPU2_CQ_PERF_MATCH 0x020 @@ -225,6 +230,15 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_CQ_C_ERR_RPT_MASK1 0x0E8 #define NPU2_CQ_C_ERR_RPT_HOLD0 0x0F0 #define NPU2_CQ_C_ERR_RPT_HOLD1 0x0F8 +#define NPU2_CQ_CTL_CONFIG_ADDR0 0x120 +#define NPU2_CQ_CTL_CONFIG_ADDR1 0x128 +#define NPU2_CQ_CTL_CONFIG_ADDR_ENABLE PPC_BIT(0) +#define NPU2_CQ_CTL_CONFIG_ADDR_STATUS PPC_BITMASK(1, 3) +#define NPU2_CQ_CTL_CONFIG_ADDR_BUS_NUMBER PPC_BITMASK(4, 11) +#define NPU2_CQ_CTL_CONFIG_ADDR_DEVICE_NUMBER PPC_BITMASK(12, 16) +#define NPU2_CQ_CTL_CONFIG_ADDR_FUNCTION_NUMBER PPC_BITMASK(17, 19) +#define NPU2_CQ_CTL_CONFIG_ADDR_REGISTER_NUMBER PPC_BITMASK(20, 31) +#define NPU2_CQ_CTL_CONFIG_ADDR_TYPE PPC_BIT(32) #define NPU2_CQ_CTL_FENCE_CONTROL_0 0x140 #define NPU2_CQ_CTL_FENCE_CONTROL_1 0x148 #define NPU2_CQ_CTL_FENCE_CONTROL_REQUEST_FENCE PPC_BITMASK(0, 1) @@ -337,9 +351,16 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_OTL_TLX_CREDITS_VC3_CREDITS PPC_BITMASK(24, 31) #define NPU2_OTL_TLX_CREDITS_DCP0_CREDITS PPC_BITMASK(32, 39) #define NPU2_OTL_TLX_CREDITS_DCP1_CREDITS PPC_BITMASK(56, 63) +#define NPU2_OTL_VC_CREDITS(stack, block) NPU2_REG_OFFSET(stack, block, 0x090) #define NPU2_OTL_CONFIG1(stack, block) NPU2_REG_OFFSET(stack, block, 0x058) +#define NPU2_OTL_CONFIG1_TX_TEMP1_EN PPC_BIT(1) +#define NPU2_OTL_CONFIG1_TX_TEMP2_EN PPC_BIT(2) +#define NPU2_OTL_CONFIG1_TX_TEMP3_EN PPC_BIT(3) #define NPU2_OTL_CONFIG1_TX_DRDY_WAIT PPC_BITMASK(5, 7) #define NPU2_OTL_CONFIG1_TX_TEMP0_RATE PPC_BITMASK(8, 11) +#define NPU2_OTL_CONFIG1_TX_TEMP1_RATE PPC_BITMASK(12, 15) +#define NPU2_OTL_CONFIG1_TX_TEMP2_RATE PPC_BITMASK(16, 19) +#define NPU2_OTL_CONFIG1_TX_TEMP3_RATE PPC_BITMASK(20, 23) #define NPU2_OTL_CONFIG1_TX_CRET_FREQ PPC_BITMASK(32, 34) #define NPU2_OTL_CONFIG1_TX_AGE_FREQ PPC_BITMASK(35, 39) #define NPU2_OTL_CONFIG1_TX_RS2_HPWAIT PPC_BITMASK(40, 45) @@ -348,6 +369,15 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_OTL_CONFIG1_TX_CBUF_ECC_DIS PPC_BIT(58) #define NPU2_OTL_CONFIG1_TX_STOP_LINK PPC_BIT(59) #define NPU2_OTL_CONFIG1_TX_STOP_ON_UE PPC_BIT(60) +#define NPU2_OTL_CONFIG1_TX_T0_MASK_CRTN0 PPC_BIT(61) +#define NPU2_OTL_CONFIG1_TX_T123_MASK_CRTN0 PPC_BIT(62) +#define NPU2_OTL_CONFIG2(stack, block) NPU2_REG_OFFSET(stack, block, 0x0C0) +#define NPU2_OTL_CONFIG2_TX_SEND_EN PPC_BIT(0) + +#define NPU2_OTL_OSL_DSISR(stack, block) NPU2_REG_OFFSET(stack, block, 0x000) +#define NPU2_OTL_OSL_DAR(stack, block) NPU2_REG_OFFSET(stack, block, 0x008) +#define NPU2_OTL_OSL_TFC(stack, block) NPU2_REG_OFFSET(stack, block, 0x010) +#define NPU2_OTL_OSL_PEHANDLE(stack, block) NPU2_REG_OFFSET(stack, block, 0x018) /* Misc block registers. Unlike the SM/CTL/DAT/NTL registers above * there is only a single instance of each of these in the NPU so we @@ -668,6 +698,26 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) +#define OB0_ODL0_CONFIG 0x901082A +#define OB0_ODL1_CONFIG 0x901082B +#define OB3_ODL0_CONFIG 0xC01082A +#define OB3_ODL1_CONFIG 0xC01082B +#define OB_ODL_CONFIG_RESET PPC_BIT(0) +#define OB_ODL_CONFIG_VERSION PPC_BITMASK(2, 7) +#define OB_ODL_CONFIG_TRAIN_MODE PPC_BITMASK(8, 11) +#define OB_ODL_CONFIG_SUPPORTED_MODES PPC_BITMASK(12, 15) +#define OB_ODL_CONFIG_X4_BACKOFF_ENABLE PPC_BIT(16) +#define OB_ODL_CONFIG_PHY_CNTR_LIMIT PPC_BITMASK(20, 23) +#define OB_ODL_CONFIG_DEBUG_ENABLE PPC_BIT(33) +#define OB_ODL_CONFIG_FWD_PROGRESS_TIMER PPC_BITMASK(40, 43) + +#define OB0_ODL0_STATUS 0x901082C +#define OB0_ODL1_STATUS 0x901082D +#define OB3_ODL0_STATUS 0xC01082C +#define OB3_ODL1_STATUS 0xC01082D +#define OB_ODL_STATUS_TRAINED_MODE PPC_BITMASK(0,3) +#define OB_ODL_STATUS_TRAINING_STATE_MACHINE PPC_BITMASK(49, 51) + #define OB0_ODL0_TRAINING_STATUS 0x901082E #define OB0_ODL1_TRAINING_STATUS 0x901082F #define OB3_ODL0_TRAINING_STATUS 0xC01082E diff --git a/include/npu2.h b/include/npu2.h index 58edf701..a48b0ac6 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -210,5 +210,10 @@ bool is_p9dd1(void); void npu2_opencapi_phy_setup(struct npu2_dev *dev); void npu2_opencapi_phy_prbs31(struct npu2_dev *dev); void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev); - +int64_t npu2_freeze_status(struct phb *phb __unused, + uint64_t pe_number __unused, + uint8_t *freeze_state, + uint16_t *pci_error_type __unused, + uint16_t *severity __unused, + uint64_t *phb_status __unused); #endif /* __NPU2_H */ |
