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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2018-03-01 15:45:51 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-03-12 21:35:51 -0500 |
| commit | 105d80f85b071e1aefefaa4e15beaee027a45fd6 (patch) | |
| tree | c5ab8671f2f7642969a185c09fa86cea4b5f77e1 /include | |
| parent | a8e6cc3f47525f86ef1d69d69a477b6264d0f8ee (diff) | |
| download | talos-skiboot-105d80f85b071e1aefefaa4e15beaee027a45fd6.tar.gz talos-skiboot-105d80f85b071e1aefefaa4e15beaee027a45fd6.zip | |
npu2: Use unfiltered mode in XTS tables
The XTS_PID context table is limited to 256 possible pids/contexts. To
relieve this limitation, make use of "unfiltered mode" instead.
If an entry in the XTS_BDF table has the bit for unfiltered mode set, we
can just use one context for that entire bdf/lpar, regardless of pid.
Instead of of searching the XTS_PID table, the NMMU checkout request
will simply use the entry indexed by lparshort id instead.
Change opal_npu_init_context() to create these lparshort-indexed
wildcard entries (0-15) instead of allocating one for each pid. Check
that multiple calls for the same bdf all specify the same msr value.
In opal_npu_destroy_context(), continue validating the bdf argument,
ensuring that it actually maps to an lpar, but no longer remove anything
from the XTS_PID table. If/when we start supporting virtualized GPUs, we
might consider actually removing these wildcard entries by keeping a
refcount, but keep things simple for now.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu2-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index db6e2795..e52918db 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -529,6 +529,7 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_XTS_MMIO_ATSD7_LPARID NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x138) #define NPU2_XTS_BDF_MAP NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x4000) #define NPU2_XTS_BDF_MAP_VALID PPC_BIT(0) +#define NPU2_XTS_BDF_MAP_UNFILT PPC_BIT(1) #define NPU2_XTS_BDF_MAP_STACK PPC_BITMASK(4, 6) #define NPU2_XTS_BDF_MAP_BRICK PPC_BIT(7) #define NPU2_XTS_BDF_MAP_BDF PPC_BITMASK(16, 31) @@ -541,6 +542,7 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_XTS_PID_MAP_VALID_ATRGPA0 PPC_BIT(0) #define NPU2_XTS_PID_MAP_VALID_ATRGPA1 PPC_BIT(1) #define NPU2_XTS_PID_MAP_VALID_ATSD PPC_BIT(2) +#define NPU2_XTS_PID_MAP_MSR PPC_BITMASK(25,31) #define NPU2_XTS_PID_MAP_MSR_DR PPC_BIT(25) #define NPU2_XTS_PID_MAP_MSR_TA PPC_BIT(26) #define NPU2_XTS_PID_MAP_MSR_HV PPC_BIT(27) |
