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| author | Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 2018-04-16 23:04:23 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-04-17 03:52:10 -0500 |
| commit | 5362f85e04bd1b03d94711c62c20de3111234f25 (patch) | |
| tree | c8a801cdf38ab6e0e53b7243ad6f825ea8612925 /include | |
| parent | 377cd39bc5e148cd84d766f0b3324a5979d4558e (diff) | |
| download | talos-skiboot-5362f85e04bd1b03d94711c62c20de3111234f25.tar.gz talos-skiboot-5362f85e04bd1b03d94711c62c20de3111234f25.zip | |
opal/hmi: check thread 0 tfmr to validate latched tfmr errors.
Due to P9 errata, HDEC parity and TB residue errors are latched for
non-zero threads 1-3 even if they are cleared. But these are not
latched on thread 0. Hence, use xscom SCOMC/SCOMD to read thread 0 tfmr
value and ignore them on non-zero threads if they are not present on
thread 0.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xscom-p9-regs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/xscom-p9-regs.h b/include/xscom-p9-regs.h index 4738e812..c3322499 100644 --- a/include/xscom-p9-regs.h +++ b/include/xscom-p9-regs.h @@ -21,4 +21,12 @@ #define P9_GPIO_DATA_OUT_ENABLE 0x00000000000B0054ull #define P9_GPIO_DATA_OUT 0x00000000000B0051ull +/* xscom address for SCOM Control and data Register */ +/* bits 54:60 of SCOM SPRC register is used for core specific SPR selection. */ +#define P9_SCOM_SPRC 0x20010A80 +#define P9_SCOMC_SPR_SELECT PPC_BITMASK(54, 60) +#define P9_SCOMC_TFMR_T0 0x8 /* 0b0001000 TFMR */ + +#define P9_SCOM_SPRD 0x20010A81 + #endif /* __XSCOM_P9_REGS_H__ */ |
