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| author | Oliver O'Halloran <oohall@gmail.com> | 2017-01-13 17:56:19 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-01-16 10:55:11 +1100 |
| commit | 7c860f25e4e44b046ee44eac9e2e0834fd4a3dbc (patch) | |
| tree | e2515e8422d24ef53a8821d91216caf1545b30a4 /hdata/test | |
| parent | 3dadd152b06756ae3dafa21d579885d9bff5a27e (diff) | |
| download | talos-skiboot-7c860f25e4e44b046ee44eac9e2e0834fd4a3dbc.tar.gz talos-skiboot-7c860f25e4e44b046ee44eac9e2e0834fd4a3dbc.zip | |
hdat: Rework service procesor information parsing
With OpenPower machines using HDAT on P9 the SPINFO structures have been
amended to support BMCs in addition to the FSP. This patch reworks the
existing parsing to prepare for adding BMC support.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[stewart@linux.vnet.ibm.com: s/UNK/UNKNOWN/ suggested by Vasant]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hdata/test')
| -rw-r--r-- | hdata/test/p8-840-spira.dt | 2 | ||||
| -rw-r--r-- | hdata/test/p81-811.spira.dt | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/hdata/test/p8-840-spira.dt b/hdata/test/p8-840-spira.dt index 79e43af4..7566e9ce 100644 --- a/hdata/test/p8-840-spira.dt +++ b/hdata/test/p8-840-spira.dt @@ -26,7 +26,7 @@ XSCOM: Found HW ID 0x0 (PCID 0x0) @ 0x3c0000000000 VPD: CCIN desc not available for : 54E1 XSCOM: Found HW ID 0x1 (PCID 0x1) @ 0x3c0800000000 VPD: CCIN desc not available for : 54E1 -FSP #0: FSP HW version 2, SW version 1, chip DD1.0 +FSP #0: HW version 2, SW version 1, chip DD1.0 CEC: HUB FRU 0 is CPU Card CEC: 2 chips in FRU CEC: Murano ! diff --git a/hdata/test/p81-811.spira.dt b/hdata/test/p81-811.spira.dt index 6098ef4a..a98cc46e 100644 --- a/hdata/test/p81-811.spira.dt +++ b/hdata/test/p81-811.spira.dt @@ -71,7 +71,7 @@ XSCOM: Found HW ID 0x10 (PCID 0x2) @ 0x3c8000000000 VPD: CCIN desc not available for : 54E8 XSCOM: Found HW ID 0x11 (PCID 0x3) @ 0x3c8800000000 VPD: CCIN desc not available for : 54E8 -FSP #0: FSP HW version 2, SW version 1, chip DD1.0 +FSP #0: HW version 2, SW version 1, chip DD1.0 CEC: HUB FRU 0 is CPU Card CEC: 2 chips in FRU CEC: Murano ! |
