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authorPhilippe Bergheaud <felix@linux.vnet.ibm.com>2018-02-21 13:31:18 +0100
committerStewart Smith <stewart@linux.vnet.ibm.com>2018-03-01 20:36:53 -0600
commit0f3584d846629d5bc1832a1dc4663a1befe8c4b0 (patch)
treed595bffde3a36b08568ac08885e6236839269333 /core
parenta8cfb0906643a7b074a5822bb312bf7481625905 (diff)
downloadtalos-skiboot-0f3584d846629d5bc1832a1dc4663a1befe8c4b0.tar.gz
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phb4: set PBCQ Tunnel BAR for tunneled operations
P9 supports PCI tunneled operations (atomics and as_notify) that are initiated by devices. A subset of the tunneled operations require a response, that must be sent back from the host to the device. For example, an atomic compare and swap will return the compare status, as swap will only performed in case of success. Similarly, as_notify reports if the target thread has been woken up or not, because the operation may fail. To enable tunneled operations, a device driver must tell the host where it expects tunneled operation responses, by setting the PBCQ Tunnel BAR Response register with a specific value within the range of its BARs. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also operate in PCI mode, a new API is required to set the PBCQ Tunnel BAR Response register, without switching to CAPI mode. This patch provides two new OPAL calls to get/set the PBCQ Tunnel BAR Response register. Note: as there is only one PBCQ Tunnel BAR register, shared between all the devices connected to the same PHB, only one of these devices will be able to use tunneled operations, at any time. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core')
-rw-r--r--core/pci-opal.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/core/pci-opal.c b/core/pci-opal.c
index b8aec941..77e965cc 100644
--- a/core/pci-opal.c
+++ b/core/pci-opal.c
@@ -1016,3 +1016,39 @@ static int64_t opal_pci_set_p2p(uint64_t phbid_init, uint64_t phbid_target,
return OPAL_SUCCESS;
}
opal_call(OPAL_PCI_SET_P2P, opal_pci_set_p2p, 4);
+
+static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr)
+{
+ struct phb *phb = pci_get_phb(phb_id);
+
+ if (!opal_addr_valid(addr))
+ return OPAL_PARAMETER;
+
+ if (!phb)
+ return OPAL_PARAMETER;
+ if (!phb->ops->get_tunnel_bar)
+ return OPAL_UNSUPPORTED;
+
+ phb_lock(phb);
+ phb->ops->get_tunnel_bar(phb, addr);
+ phb_unlock(phb);
+ return OPAL_SUCCESS;
+}
+opal_call(OPAL_PCI_GET_PBCQ_TUNNEL_BAR, opal_pci_get_pbcq_tunnel_bar, 2);
+
+static int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr)
+{
+ struct phb *phb = pci_get_phb(phb_id);
+ int64_t rc;
+
+ if (!phb)
+ return OPAL_PARAMETER;
+ if (!phb->ops->set_tunnel_bar)
+ return OPAL_UNSUPPORTED;
+
+ phb_lock(phb);
+ rc = phb->ops->set_tunnel_bar(phb, addr);
+ phb_unlock(phb);
+ return rc;
+}
+opal_call(OPAL_PCI_SET_PBCQ_TUNNEL_BAR, opal_pci_set_pbcq_tunnel_bar, 2);
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