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authorVasant Hegde <hegdevasant@linux.vnet.ibm.com>2018-04-23 12:15:32 +0530
committerStewart Smith <stewart@linux.ibm.com>2018-04-30 19:04:42 -0500
commitd7e7bdcd4accff9fb75579b43be72bc3c201d161 (patch)
tree0641e6c0ec772449322c053024a70da759d51a24 /core/test
parent6421fc56dc289c8d14a1ce9eddbb88d3687fbb77 (diff)
downloadtalos-skiboot-d7e7bdcd4accff9fb75579b43be72bc3c201d161.tar.gz
talos-skiboot-d7e7bdcd4accff9fb75579b43be72bc3c201d161.zip
SBE: Add timer support
SBE on P9 provides one shot programmable timer facility. We can use this to implement OPAL timers and hence limit the reliance on the Linux heartbeat (similar to HW timer facility provided by SLW on P8). Design: - We will continue to run Linux heartbeat. - Each chip has SBE. This patch always schedules timer on SBE on master chip. - Start timer option starts new timer or modifies an active timer for the specified timeout. - SBE expects timeout value in microseconds. We track timeout value in TB. Hence we convert tb to microseconds before sending request to SBE. - We are requesting ack from SBE for timer message. It gaurantees that SBE has scheduled timer. - Disabling SBE timer We expect SBE to send timer expiry interrupt whenever timer expires. We wait for 10 more ms before disabling timer. In future we can consider below alternative approaches: - Presently SBE timer disable is permanent (until we reboot system). SBE sends "I'm back" interrupt after reset. We can consider restarting timer after SBE reset. - Reset SBE and start timer again. - Each chip has SBE. On multi chip system we can try to schedule timer on different chip. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'core/test')
-rw-r--r--core/test/run-timer.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/core/test/run-timer.c b/core/test/run-timer.c
index 986af28d..159e007a 100644
--- a/core/test/run-timer.c
+++ b/core/test/run-timer.c
@@ -4,12 +4,15 @@
#define __TEST__
#include <timer.h>
+#include <skiboot.h>
#define mftb() (stamp)
#define sync()
#define smt_lowest()
#define smt_medium()
+enum proc_gen proc_gen = proc_gen_p9;
+
static uint64_t stamp, last;
struct lock;
static inline void lock_caller(struct lock *l, const char *caller)
@@ -53,6 +56,11 @@ void p8_sbe_update_timer_expiry(uint64_t new_target)
/* FIXME: do intersting SLW timer sim */
}
+void p9_sbe_update_timer_expiry(uint64_t new_target)
+{
+ (void)new_target;
+}
+
int main(void)
{
unsigned int i;
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